Hi all
I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation
purpose I need to reduce the clock frequency and measure the time that my
algorithm needs. Now first question: How can I reduce the clock frequency for
the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)"
in the DSP/BIOS config tool. But I'm not really sure if the change
I've made had any effect because the execution times I've measured
were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both
in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking
at SPI signals on the scope since SPI is only active after the algo
completes.
Could you please tell me if there are any problems with clock frequency
reduction like I do it or with the time measurement in software? Anyway, the
time measurements on the scope and in software correlate well enough, so I think
it's either a problem in clock frequency reduction or my algorithm performs
well (but this would be strange).;)
Last question: does reducing the DSP clock frequency have an influence on
SPI?
Thanks for all your help
Andreas
_____________________________________
Clock frequency reduction
Started by ●August 10, 2010
Reply by ●August 10, 20102010-08-10
Hello Andreas,
On Tue, Aug 10, 2010 at 9:41 AM, wrote:
> Hi all
>
> I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation
> purpose I need to reduce the clock frequency and measure the time that my
> algorithm needs. Now first question: How can I reduce the clock frequency
> for the C6747?
>
The first info that you need is in sprufk4 [TMS320C6745-C6747DSPSystem].
This will explain how to program the PLL for clock freq changes and 'a bunch
of other stuff about clock requirements and interactions'.
> All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS
> config tool.
>
This is not a 'control setting' - it is an 'information setting' for the
DSP-BIOS.
When you reprogram the PLL, you should enter the new speed here.
> But I'm not really sure if the change I've made had any effect because the
> execution times I've measured were quasi the same for 300 MHz, 200 MHz or
> even 10 MHz. I've measured both in software using CLK_getltime() *
> CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope
> since SPI is only active after the algo completes.
>
> Could you please tell me if there are any problems with clock frequency
> reduction like I do it or with the time measurement in software? Anyway, the
> time measurements on the scope and in software correlate well enough, so I
> think it's either a problem in clock frequency reduction or my algorithm
> performs well (but this would be strange).;)
>
> Last question: does reducing the DSP clock frequency have an influence on
> SPI?
>
Not usually.
Reduced freq will give you fewer execution cycles per SPI transfer and
slower interrupt response time. This is not usually 'noticed' by SPI, unless
the freq gets really low and/or you have chunks of 'disabled interrupt
code' that could affect SPI servicing.
mikedunn
>
> Thanks for all your help
>
> Andreas
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Tue, Aug 10, 2010 at 9:41 AM, wrote:
> Hi all
>
> I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation
> purpose I need to reduce the clock frequency and measure the time that my
> algorithm needs. Now first question: How can I reduce the clock frequency
> for the C6747?
>
The first info that you need is in sprufk4 [TMS320C6745-C6747DSPSystem].
This will explain how to program the PLL for clock freq changes and 'a bunch
of other stuff about clock requirements and interactions'.
> All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS
> config tool.
>
This is not a 'control setting' - it is an 'information setting' for the
DSP-BIOS.
When you reprogram the PLL, you should enter the new speed here.
> But I'm not really sure if the change I've made had any effect because the
> execution times I've measured were quasi the same for 300 MHz, 200 MHz or
> even 10 MHz. I've measured both in software using CLK_getltime() *
> CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope
> since SPI is only active after the algo completes.
>
> Could you please tell me if there are any problems with clock frequency
> reduction like I do it or with the time measurement in software? Anyway, the
> time measurements on the scope and in software correlate well enough, so I
> think it's either a problem in clock frequency reduction or my algorithm
> performs well (but this would be strange).;)
>
> Last question: does reducing the DSP clock frequency have an influence on
> SPI?
>
Not usually.
Reduced freq will give you fewer execution cycles per SPI transfer and
slower interrupt response time. This is not usually 'noticed' by SPI, unless
the freq gets really low and/or you have chunks of 'disabled interrupt
code' that could affect SPI servicing.
mikedunn
>
> Thanks for all your help
>
> Andreas
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●August 10, 20102010-08-10
andreas,
I'm not familiar with the c6747, so the following comments are 'general'
The clock frequency is set by the parameters used for initialization of the PLL.
When the PLL frequency is modified, then all communication frequency setup parameters
need to be modified to compensate for the PLL frequency change, including the SPI.
in the DSP, the clkout frequency is via a divider/multiplier to derive the desired
frequency from the PLL/CPU clock frequency.
From you post, I think you are using the BIOS.
Therefore, you will need to modify the appropriate parameters in the configuration file
for the BIOS.
This will not be the parameters for the setup of the clkout frequency.
I'm not familiar enough with the BIOS configuration file to state exactly which
parameters need to be modified, but I would expect it to be related to the PLL
initialization.
R. Williams
---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Tue, 10 Aug 2010 10:41:31 -0400
Subject: [c6x] Clock frequency reduction
> Hi all
>
> I'm working with the OMAP-L137 EVM and only use the C6747. For
> evaluation purpose I need to reduce the clock frequency and measure
> the time that my algorithm needs. Now first question: How can I reduce
> the clock frequency for the C6747? All I've done is I've changed "DSP
> speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really
> sure if the change I've made had any effect because the execution
> times I've measured were quasi the same for 300 MHz, 200 MHz or even
> 10 MHz. I've measured both in software using CLK_getltime() *
> CLK_getprd() / CLK_countspms() and by looking at SPI signals on the
> scope since SPI is only active after the algo completes.
>
> Could you please tell me if there are any problems with clock
> frequency reduction like I do it or with the time measurement in
> software? Anyway, the time measurements on the scope and in software
> correlate well enough, so I think it's either a problem in clock
> frequency reduction or my algorithm performs well (but this would be
> strange).;)
>
> Last question: does reducing the DSP clock frequency have an influence
> on SPI?
>
> Thanks for all your help
>
> Andreas
------- End of Original Message -------
_____________________________________
I'm not familiar with the c6747, so the following comments are 'general'
The clock frequency is set by the parameters used for initialization of the PLL.
When the PLL frequency is modified, then all communication frequency setup parameters
need to be modified to compensate for the PLL frequency change, including the SPI.
in the DSP, the clkout frequency is via a divider/multiplier to derive the desired
frequency from the PLL/CPU clock frequency.
From you post, I think you are using the BIOS.
Therefore, you will need to modify the appropriate parameters in the configuration file
for the BIOS.
This will not be the parameters for the setup of the clkout frequency.
I'm not familiar enough with the BIOS configuration file to state exactly which
parameters need to be modified, but I would expect it to be related to the PLL
initialization.
R. Williams
---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Tue, 10 Aug 2010 10:41:31 -0400
Subject: [c6x] Clock frequency reduction
> Hi all
>
> I'm working with the OMAP-L137 EVM and only use the C6747. For
> evaluation purpose I need to reduce the clock frequency and measure
> the time that my algorithm needs. Now first question: How can I reduce
> the clock frequency for the C6747? All I've done is I've changed "DSP
> speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really
> sure if the change I've made had any effect because the execution
> times I've measured were quasi the same for 300 MHz, 200 MHz or even
> 10 MHz. I've measured both in software using CLK_getltime() *
> CLK_getprd() / CLK_countspms() and by looking at SPI signals on the
> scope since SPI is only active after the algo completes.
>
> Could you please tell me if there are any problems with clock
> frequency reduction like I do it or with the time measurement in
> software? Anyway, the time measurements on the scope and in software
> correlate well enough, so I think it's either a problem in clock
> frequency reduction or my algorithm performs well (but this would be
> strange).;)
>
> Last question: does reducing the DSP clock frequency have an influence
> on SPI?
>
> Thanks for all your help
>
> Andreas
------- End of Original Message -------
_____________________________________
Reply by ●August 10, 20102010-08-10
Hi Mike, Richard and Franz
Thanks a lot for your replies. Together with the help from Mike I've realized that in CCS there's a .gel file to do PLL set up. The values therein (in particular PLLM and POSTDIV) can be directly modified for evaluation purposes or the setup_pll() function and all the #define directives it needs can be copied to source code. I didn't find any appropriate settings in BIOS config. Apparently, changing the CLKOUT directly in the BIOS settings does not change anything in the PLL registers, as Richard suggested.
Best regards,
Andreas
Hi all
>
>I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I need to reduce the clock frequency and measure the time that my algorithm needs. Now first question: How can I reduce the clock frequency for the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really sure if the change I've made had any effect because the execution times I've measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope since SPI is only active after the algo completes.
>
>Could you please tell me if there are any problems with clock frequency reduction like I do it or with the time measurement in software? Anyway, the time measurements on the scope and in software correlate well enough, so I think it's either a problem in clock frequency reduction or my algorithm performs well (but this would be strange).;)
>
>Last question: does reducing the DSP clock frequency have an influence on SPI?
>
>Thanks for all your help
>
>Andreas
>
>_____________________________________
_____________________________________
Thanks a lot for your replies. Together with the help from Mike I've realized that in CCS there's a .gel file to do PLL set up. The values therein (in particular PLLM and POSTDIV) can be directly modified for evaluation purposes or the setup_pll() function and all the #define directives it needs can be copied to source code. I didn't find any appropriate settings in BIOS config. Apparently, changing the CLKOUT directly in the BIOS settings does not change anything in the PLL registers, as Richard suggested.
Best regards,
Andreas
Hi all
>
>I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I need to reduce the clock frequency and measure the time that my algorithm needs. Now first question: How can I reduce the clock frequency for the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really sure if the change I've made had any effect because the execution times I've measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope since SPI is only active after the algo completes.
>
>Could you please tell me if there are any problems with clock frequency reduction like I do it or with the time measurement in software? Anyway, the time measurements on the scope and in software correlate well enough, so I think it's either a problem in clock frequency reduction or my algorithm performs well (but this would be strange).;)
>
>Last question: does reducing the DSP clock frequency have an influence on SPI?
>
>Thanks for all your help
>
>Andreas
>
>_____________________________________
_____________________________________
Reply by ●August 10, 20102010-08-10
> Subject: Re: Clock frequency reduction
> Posted by: andreas.we...
> Date: Tue Aug 10, 2010 11:13 am ((PDT))
>
> Thanks a lot for your replies. Together with the help from Mike I've
> realized that in CCS there's a .gel file to do PLL set up. The values therein
> (in particular PLLM and POSTDIV) can be directly modified for evaluation
> purposes or the setup_pll() function and all the #define directives it needs
> can be copied to source code. I didn't find any appropriate settings in BIOS
> config. Apparently, changing the CLKOUT directly in the BIOS settings does
> not change anything in the PLL registers, as Richard suggested.
Hi Andreas,
A few caveats: L137 is a dual-CPU device, where all low-level inits are being
done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible for a
program running on the DSP (C67+) side.
Similarly, there should be two .gel scripts; each for the corresponding CPU.
It might be possible though to set PLLs, PSC and DDR in the .gel script for
the DSP side since the script is interpreted and applied to the device via
the JTAG interface; however I am not sure. I always did this in the .gel
script for the ARM side in the DM644x/DM646x devices.
Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
simply because it runs on the DSP side. In order to perform low-level init
you have to boot the ARM side and after the low-level init has been done the
ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP from
reset. This is the "no-emulation" scenario...
For the documentation, you might want to start with SPRU190 in the OMAP section
and look at SPRUFK5 and SPRUG84 user's guides.
Rgds,
Andrew
_____________________________________
> Posted by: andreas.we...
> Date: Tue Aug 10, 2010 11:13 am ((PDT))
>
> Thanks a lot for your replies. Together with the help from Mike I've
> realized that in CCS there's a .gel file to do PLL set up. The values therein
> (in particular PLLM and POSTDIV) can be directly modified for evaluation
> purposes or the setup_pll() function and all the #define directives it needs
> can be copied to source code. I didn't find any appropriate settings in BIOS
> config. Apparently, changing the CLKOUT directly in the BIOS settings does
> not change anything in the PLL registers, as Richard suggested.
Hi Andreas,
A few caveats: L137 is a dual-CPU device, where all low-level inits are being
done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible for a
program running on the DSP (C67+) side.
Similarly, there should be two .gel scripts; each for the corresponding CPU.
It might be possible though to set PLLs, PSC and DDR in the .gel script for
the DSP side since the script is interpreted and applied to the device via
the JTAG interface; however I am not sure. I always did this in the .gel
script for the ARM side in the DM644x/DM646x devices.
Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
simply because it runs on the DSP side. In order to perform low-level init
you have to boot the ARM side and after the low-level init has been done the
ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP from
reset. This is the "no-emulation" scenario...
For the documentation, you might want to start with SPRU190 in the OMAP section
and look at SPRUFK5 and SPRUG84 user's guides.
Rgds,
Andrew
_____________________________________
Reply by ●August 11, 20102010-08-11
Hello Andrew,
In the spirit of 'correct information', I must disagree with some of your
comments.
see below.
On Tue, Aug 10, 2010 at 3:24 PM, Andrew Nesterov <
a...@techemail.com> wrote:
>
> > Subject: Re: Clock frequency reduction
> > Posted by: andreas.we...
> > Date: Tue Aug 10, 2010 11:13 am ((PDT))
> >
> > Thanks a lot for your replies. Together with the help from Mike I've
> > realized that in CCS there's a .gel file to do PLL set up. The values
> therein
> > (in particular PLLM and POSTDIV) can be directly modified for evaluation
> > purposes or the setup_pll() function and all the #define directives it
> needs
> > can be copied to source code. I didn't find any appropriate settings in
> BIOS
> > config. Apparently, changing the CLKOUT directly in the BIOS settings
> does
> > not change anything in the PLL registers, as Richard suggested.
>
> Hi Andreas,
>
> A few caveats: L137 is a dual-CPU device, where all low-level inits are
> being
> done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible
> for a
> program running on the DSP (C67+) side.
>
This is not true. The full range of common peripherals are accessible from
each device.
Many [most??] ARM/DSP implementations that I have seen attempt to put only
[or close to it] algorithm processing on the DSP and have the ARM handle the
UI+HighLevelApp+OS+AnyRequiredGruntWork.
As I understand it, L137 platforms are being endorsed for C6747 development
[same DSP - no ARM]. I assume [?] that is what Andreas is trying to
accomplish.
Andreas, you are on the right track.
mikedunn
>
> Similarly, there should be two .gel scripts; each for the corresponding
> CPU.
> It might be possible though to set PLLs, PSC and DDR in the .gel script for
> the DSP side since the script is interpreted and applied to the device via
> the JTAG interface; however I am not sure. I always did this in the .gel
> script for the ARM side in the DM644x/DM646x devices.
>
> Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
> simply because it runs on the DSP side. In order to perform low-level init
> you have to boot the ARM side and after the low-level init has been done
> the
> ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP
> from
> reset. This is the "no-emulation" scenario...
>
> For the documentation, you might want to start with SPRU190 in the OMAP
> section
> and look at SPRUFK5 and SPRUG84 user's guides.
>
> Rgds,
>
> Andrew
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
In the spirit of 'correct information', I must disagree with some of your
comments.
see below.
On Tue, Aug 10, 2010 at 3:24 PM, Andrew Nesterov <
a...@techemail.com> wrote:
>
> > Subject: Re: Clock frequency reduction
> > Posted by: andreas.we...
> > Date: Tue Aug 10, 2010 11:13 am ((PDT))
> >
> > Thanks a lot for your replies. Together with the help from Mike I've
> > realized that in CCS there's a .gel file to do PLL set up. The values
> therein
> > (in particular PLLM and POSTDIV) can be directly modified for evaluation
> > purposes or the setup_pll() function and all the #define directives it
> needs
> > can be copied to source code. I didn't find any appropriate settings in
> BIOS
> > config. Apparently, changing the CLKOUT directly in the BIOS settings
> does
> > not change anything in the PLL registers, as Richard suggested.
>
> Hi Andreas,
>
> A few caveats: L137 is a dual-CPU device, where all low-level inits are
> being
> done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible
> for a
> program running on the DSP (C67+) side.
>
This is not true. The full range of common peripherals are accessible from
each device.
Many [most??] ARM/DSP implementations that I have seen attempt to put only
[or close to it] algorithm processing on the DSP and have the ARM handle the
UI+HighLevelApp+OS+AnyRequiredGruntWork.
As I understand it, L137 platforms are being endorsed for C6747 development
[same DSP - no ARM]. I assume [?] that is what Andreas is trying to
accomplish.
Andreas, you are on the right track.
mikedunn
>
> Similarly, there should be two .gel scripts; each for the corresponding
> CPU.
> It might be possible though to set PLLs, PSC and DDR in the .gel script for
> the DSP side since the script is interpreted and applied to the device via
> the JTAG interface; however I am not sure. I always did this in the .gel
> script for the ARM side in the DM644x/DM646x devices.
>
> Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
> simply because it runs on the DSP side. In order to perform low-level init
> you have to boot the ARM side and after the low-level init has been done
> the
> ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP
> from
> reset. This is the "no-emulation" scenario...
>
> For the documentation, you might want to start with SPRU190 in the OMAP
> section
> and look at SPRUFK5 and SPRUG84 user's guides.
>
> Rgds,
>
> Andrew
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●August 11, 20102010-08-11
Hi Mike,
Thanks for pointing this out. After careful reading of SPRUG84 I have
to agree with your comments. My reasoning "by similarity" (wrt DM6446
and DM6467 devices) has proved to be apparently wrong...
Cheers,
Andrew
> Date: Tue, 10 Aug 2010 23:59:43 -0500
> From: Michael Dunn
>
> Hello Andrew,
>
> In the spirit of 'correct information', I must disagree with some of your
> comments.
> see below.
>
> On Tue, Aug 10, 2010 at 3:24 PM, Andrew Nesterov wrote:
>>
>>> Subject: Re: Clock frequency reduction
>>> Posted by: andreas.we...
>>> Date: Tue Aug 10, 2010 11:13 am ((PDT))
>>>
>>> Thanks a lot for your replies. Together with the help from Mike I've
>>> realized that in CCS there's a .gel file to do PLL set up. The values
>> therein
>>> (in particular PLLM and POSTDIV) can be directly modified for evaluation
>>> purposes or the setup_pll() function and all the #define directives it
>> needs
>>> can be copied to source code. I didn't find any appropriate settings in
>> BIOS
>>> config. Apparently, changing the CLKOUT directly in the BIOS settings
>> does
>>> not change anything in the PLL registers, as Richard suggested.
>>
>> Hi Andreas,
>>
>> A few caveats: L137 is a dual-CPU device, where all low-level inits are
>> being
>> done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible
>> for a
>> program running on the DSP (C67+) side.
>>
>
> This is not true. The full range of common peripherals are accessible from
> each device.
> Many [most??] ARM/DSP implementations that I have seen attempt to put only
> [or close to it] algorithm processing on the DSP and have the ARM handle the
> UI+HighLevelApp+OS+AnyRequiredGruntWork.
> As I understand it, L137 platforms are being endorsed for C6747 development
> [same DSP - no ARM]. I assume [?] that is what Andreas is trying to
> accomplish.
>
> Andreas, you are on the right track.
>
> mikedunn
>
>>
>> Similarly, there should be two .gel scripts; each for the corresponding
>> CPU.
>> It might be possible though to set PLLs, PSC and DDR in the .gel script for
>> the DSP side since the script is interpreted and applied to the device via
>> the JTAG interface; however I am not sure. I always did this in the .gel
>> script for the ARM side in the DM644x/DM646x devices.
>>
>> Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
>> simply because it runs on the DSP side. In order to perform low-level init
>> you have to boot the ARM side and after the low-level init has been done
>> the
>> ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP
>> from
>> reset. This is the "no-emulation" scenario...
>>
>> For the documentation, you might want to start with SPRU190 in the OMAP
>> section
>> and look at SPRUFK5 and SPRUG84 user's guides.
>>
>> Rgds,
>>
>> Andrew
>>
>>
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
_____________________________________
Thanks for pointing this out. After careful reading of SPRUG84 I have
to agree with your comments. My reasoning "by similarity" (wrt DM6446
and DM6467 devices) has proved to be apparently wrong...
Cheers,
Andrew
> Date: Tue, 10 Aug 2010 23:59:43 -0500
> From: Michael Dunn
>
> Hello Andrew,
>
> In the spirit of 'correct information', I must disagree with some of your
> comments.
> see below.
>
> On Tue, Aug 10, 2010 at 3:24 PM, Andrew Nesterov wrote:
>>
>>> Subject: Re: Clock frequency reduction
>>> Posted by: andreas.we...
>>> Date: Tue Aug 10, 2010 11:13 am ((PDT))
>>>
>>> Thanks a lot for your replies. Together with the help from Mike I've
>>> realized that in CCS there's a .gel file to do PLL set up. The values
>> therein
>>> (in particular PLLM and POSTDIV) can be directly modified for evaluation
>>> purposes or the setup_pll() function and all the #define directives it
>> needs
>>> can be copied to source code. I didn't find any appropriate settings in
>> BIOS
>>> config. Apparently, changing the CLKOUT directly in the BIOS settings
>> does
>>> not change anything in the PLL registers, as Richard suggested.
>>
>> Hi Andreas,
>>
>> A few caveats: L137 is a dual-CPU device, where all low-level inits are
>> being
>> done on the ARM side. E.g. PLLs, PSC and DDR registes are not accessible
>> for a
>> program running on the DSP (C67+) side.
>>
>
> This is not true. The full range of common peripherals are accessible from
> each device.
> Many [most??] ARM/DSP implementations that I have seen attempt to put only
> [or close to it] algorithm processing on the DSP and have the ARM handle the
> UI+HighLevelApp+OS+AnyRequiredGruntWork.
> As I understand it, L137 platforms are being endorsed for C6747 development
> [same DSP - no ARM]. I assume [?] that is what Andreas is trying to
> accomplish.
>
> Andreas, you are on the right track.
>
> mikedunn
>
>>
>> Similarly, there should be two .gel scripts; each for the corresponding
>> CPU.
>> It might be possible though to set PLLs, PSC and DDR in the .gel script for
>> the DSP side since the script is interpreted and applied to the device via
>> the JTAG interface; however I am not sure. I always did this in the .gel
>> script for the ARM side in the DM644x/DM646x devices.
>>
>> Similarly, the DSP/BIOS just cannot access both PLLs, PSC and DDR registers
>> simply because it runs on the DSP side. In order to perform low-level init
>> you have to boot the ARM side and after the low-level init has been done
>> the
>> ARM would load the DSP with e.g. a DSP/BIOS-based code and release the DSP
>> from
>> reset. This is the "no-emulation" scenario...
>>
>> For the documentation, you might want to start with SPRU190 in the OMAP
>> section
>> and look at SPRUFK5 and SPRUG84 user's guides.
>>
>> Rgds,
>>
>> Andrew
>>
>>
>> --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
_____________________________________
Reply by ●August 11, 20102010-08-11
Yeah Mike is right. By modifying the GEL file, I was able to reduce the DSP
clock frequency down to 24 MHz. :)
Best regards,
Andreas
Hi all
>
>I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I need to reduce the clock frequency and measure the time that my algorithm needs. Now first question: How can I reduce the clock frequency for the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really sure if the change I've made had any effect because the execution times I've measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope since SPI is only active after the algo completes.
>
>Could you please tell me if there are any problems with clock frequency reduction like I do it or with the time measurement in software? Anyway, the time measurements on the scope and in software correlate well enough, so I think it's either a problem in clock frequency reduction or my algorithm performs well (but this would be strange).;)
>
>Last question: does reducing the DSP clock frequency have an influence on SPI?
>
>Thanks for all your help
>
>Andreas
>
>_____________________________________
_____________________________________
Best regards,
Andreas
Hi all
>
>I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I need to reduce the clock frequency and measure the time that my algorithm needs. Now first question: How can I reduce the clock frequency for the C6747? All I've done is I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not really sure if the change I've made had any effect because the execution times I've measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI signals on the scope since SPI is only active after the algo completes.
>
>Could you please tell me if there are any problems with clock frequency reduction like I do it or with the time measurement in software? Anyway, the time measurements on the scope and in software correlate well enough, so I think it's either a problem in clock frequency reduction or my algorithm performs well (but this would be strange).;)
>
>Last question: does reducing the DSP clock frequency have an influence on SPI?
>
>Thanks for all your help
>
>Andreas
>
>_____________________________________
_____________________________________
Reply by ●August 12, 20102010-08-12
andreas,
One thing to remember is a final product will not be attached to a CCS.
Therefore, anything you do with a .GEL file to prep the DSP will need to be duplicated
in the 'main' source code.
R. Williams
---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Wed, 11 Aug 2010 07:32:51 -0400
Subject: [c6x] Re: Clock frequency reduction
> Yeah Mike is right. By modifying the GEL file, I was able to reduce
> the DSP clock frequency down to 24 MHz. :)
>
> Best regards,
> Andreas
>
> Hi all
> >
> >I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I
need to reduce the clock frequency and measure the time that my algorithm needs. Now
first question: How can I reduce the clock frequency for the C6747? All I've done is
I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not
really sure if the change I've made had any effect because the execution times I've
measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in
software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI
signals on the scope since SPI is only active after the algo completes.
> >
> >Could you please tell me if there are any problems with clock frequency reduction
like I do it or with the time measurement in software? Anyway, the time measurements on
the scope and in software correlate well enough, so I think it's either a problem in
clock frequency reduction or my algorithm performs well (but this would be strange).;)
> >
> >Last question: does reducing the DSP clock frequency have an influence on SPI?
> >
> >Thanks for all your help
> >
> >Andreas
> >
> >_____________________________________
> >
> >
------- End of Original Message -------
_____________________________________
One thing to remember is a final product will not be attached to a CCS.
Therefore, anything you do with a .GEL file to prep the DSP will need to be duplicated
in the 'main' source code.
R. Williams
---------- Original Message -----------
From: a...@gmail.com
To: c...
Sent: Wed, 11 Aug 2010 07:32:51 -0400
Subject: [c6x] Re: Clock frequency reduction
> Yeah Mike is right. By modifying the GEL file, I was able to reduce
> the DSP clock frequency down to 24 MHz. :)
>
> Best regards,
> Andreas
>
> Hi all
> >
> >I'm working with the OMAP-L137 EVM and only use the C6747. For evaluation purpose I
need to reduce the clock frequency and measure the time that my algorithm needs. Now
first question: How can I reduce the clock frequency for the C6747? All I've done is
I've changed "DSP speed in MHz (CLKOUT)" in the DSP/BIOS config tool. But I'm not
really sure if the change I've made had any effect because the execution times I've
measured were quasi the same for 300 MHz, 200 MHz or even 10 MHz. I've measured both in
software using CLK_getltime() * CLK_getprd() / CLK_countspms() and by looking at SPI
signals on the scope since SPI is only active after the algo completes.
> >
> >Could you please tell me if there are any problems with clock frequency reduction
like I do it or with the time measurement in software? Anyway, the time measurements on
the scope and in software correlate well enough, so I think it's either a problem in
clock frequency reduction or my algorithm performs well (but this would be strange).;)
> >
> >Last question: does reducing the DSP clock frequency have an influence on SPI?
> >
> >Thanks for all your help
> >
> >Andreas
> >
> >_____________________________________
> >
> >
------- End of Original Message -------
_____________________________________
