CVDD and DVDD Decoupling

Hi,

Just a couple of questions about power decoupling. I am using the TPS65023
to supply the 1.2V and 3.3V. The IC is very close to and solely supplies the
DSP. The datasheet mentions that one 100nF capacitor should be used per
power pin. Since I am using the BGA package, this means the caps must be
mounted on the bottom side of the PCB.

Two questions:

- I am I right in saying that the caps must be on the bottom side of the
board? If so, it may be difficult for me.
- Do I have to use all this capacitors? The application I am using the DSP
for is not that sensitive.

--
Kind regards,
Samir.

---------------------------
Samir Bendoukha

"Computers are like air conditioners, they stop working properly if you open
Windows." Start a New Thread

Samir-

You didn't mention which DSP, how fast it's running, how much memory (and what kind). Wouldn't you think those things
are relevant to level of effort to ensure stability of core and IO voltages?

-Jeff

> Just a couple of questions about power decoupling. I am using the TPS65023
> to supply the 1.2V and 3.3V. The IC is very close to and solely supplies the
> DSP. The datasheet mentions that one 100nF capacitor should be used per
> power pin. Since I am using the BGA package, this means the caps must be
> mounted on the bottom side of the PCB.
>
> Two questions:
>
> - I am I right in saying that the caps must be on the bottom side of the
> board? If so, it may be difficult for me.
> - Do I have to use all this capacitors? The application I am using the DSP
> for is not that sensitive.
>
> --
> Kind regards,
> Samir.
>
> ---------------------------
> Samir Bendoukha
>
> "Computers are like air conditioners, they stop working properly if you open
> Windows."
>

_____________________________________ Start a New Thread

Dear Samir,

we have built quite a number of boards with various C6000 processors. It
turned out impossible to follow TI's recomendations for power supply
decoupling *and* getting all processor signals routed out of the BGA
package. This may be barely possible by using blind and buried vias, but
not with a standard through-hole via PCB.

Nevertheless, we didn't experience any power-supply-related problems on our
boards. On the 6747 designs for example (21 DVDD pins, 18 CVDD pins), we
use 3*100n and 7*10n DVDD decoupling. For CVDD 2*100n and 5*10n are used.
These are 0603 capacitors which are placed on the bottom layer directly
underneath the DSP. It is very important to use the thickest and shortest
connections possible to keep the track impedance as low as possible. Use
only high quality caps: X7R or even NP0.
Our PCBs also use a very thin dielectric between the power and GND planes,
which provides some extra "distributed" capacitance and minimizes radiation.
Additionally we place a 10..22u X5R bulk capacitor for each supply rail
close to the DSP.
The 10n an 100n caps use up almost the entire space underneath the DSP. You
may use 0402 caps to increase the capacitor count.

Some care must be taken with "analog" supply voltages (PLL and USB): these
are highly sensitive, and you should follow TI's decoupling and filter
recomendations.

Best Regards,
Adolf Klemenz
At 13:22 26.08.2010 +0100, Samir Bendoukha wrote:
>Just a couple of questions about power decoupling. I am using the TPS65023
>to supply the 1.2V and 3.3V. The IC is very close to and solely supplies
>the DSP. The datasheet mentions that one 100nF capacitor should be used
>per power pin. Since I am using the BGA package, this means the caps must
>be mounted on the bottom side of the PCB.
>
>Two questions:
>
>- I am I right in saying that the caps must be on the bottom side of the
>board? If so, it may be difficult for me.
>- Do I have to use all this capacitors? The application I am using the DSP
>for is not that sensitive.

_____________________________________ Start a New Thread

Samir,

In addition to Jeff's comments...
The total make up of your board + 'what ever else might be on the 65023
input voltage and/or ground' is also important.
We do not know what you have - a simple board with just a DSP or a large
2 layer board with several banks of memory and some motor controllers
[an exageration to make a point].

mikedunn

On 8/26/2010 11:48 AM, Jeff Brower wrote:
>
> Samir-
>
> You didn't mention which DSP, how fast it's running, how much memory
> (and what kind). Wouldn't you think those things
> are relevant to level of effort to ensure stability of core and IO
> voltages?
>
> -Jeff
>
> > Just a couple of questions about power decoupling. I am using the
> TPS65023
> > to supply the 1.2V and 3.3V. The IC is very close to and solely
> supplies the
> > DSP. The datasheet mentions that one 100nF capacitor should be used per
> > power pin. Since I am using the BGA package, this means the caps must be
> > mounted on the bottom side of the PCB.
> >
> > Two questions:
> >
> > - I am I right in saying that the caps must be on the bottom side of the
> > board? If so, it may be difficult for me.
> > - Do I have to use all this capacitors? The application I am using
> the DSP
> > for is not that sensitive.
> >
> > --
> > Kind regards,
> > Samir.
> >
> > ---------------------------
> > Samir Bendoukha
> >
> > "Computers are like air conditioners, they stop working properly if
> you open
> > Windows."
> > Start a New Thread

*Adolf,*

Thanks for the insight.
*Jeff and Mike,
*
Sorry, I forgot to give more details. My board is very simple. I am using
the C6747 to perform pulse detection and characterisation (using a dual
channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
some analogue outputs.

- The TPS is sitting right next to the DSP and I am using the same design as
in the OMAP137 EVM.
- There is no external memory.
- The DSP will be running at 300MHz, although I think it might be a bit
excessive and might end up reducing it.

Thanks for the help guys.
Kind regards,
Samir.
On 26 August 2010 22:50, mikedunn wrote:

> Samir,
>
> In addition to Jeff's comments...
> The total make up of your board + 'what ever else might be on the 65023
> input voltage and/or ground' is also important.
> We do not know what you have - a simple board with just a DSP or a large 2
> layer board with several banks of memory and some motor controllers [an
> exageration to make a point].
>
> mikedunn
> On 8/26/2010 11:48 AM, Jeff Brower wrote:
>
> Samir-
>
> You didn't mention which DSP, how fast it's running, how much memory (and
> what kind). Wouldn't you think those things
> are relevant to level of effort to ensure stability of core and IO
> voltages?
>
> -Jeff
>
> > Just a couple of questions about power decoupling. I am using the
> TPS65023
> > to supply the 1.2V and 3.3V. The IC is very close to and solely supplies
> the
> > DSP. The datasheet mentions that one 100nF capacitor should be used per
> > power pin. Since I am using the BGA package, this means the caps must be
> > mounted on the bottom side of the PCB.
> >
> > Two questions:
> >
> > - I am I right in saying that the caps must be on the bottom side of the
> > board? If so, it may be difficult for me.
> > - Do I have to use all this capacitors? The application I am using the
> DSP
> > for is not that sensitive.
> >
> > --
> > Kind regards,
> > Samir.
> >
> > ---------------------------
> > Samir Bendoukha
> >
> > "Computers are like air conditioners, they stop working properly if you
> open
> > Windows."
> >
>
--
Kind regards,
Samir.

---------------------------
Samir Bendoukha

"Computers are like air conditioners, they stop working properly if you open
Windows."

_____________________________________ Start a New Thread

Samir,

Adolf's suggestions are probably adequate. Personally, I try to make as
many provisions as reasonable [as determined by TI suggestions, which
are usually worst case, and my experience] for filtering when the board
is laid out. This is because it it such a pain to add caps after the fact.

I am not sure of your experience level, so I will add the following...
When I bring up a new design - especially if I have not worked with the
device previously - I try to take the time to look at power, clocks, and
external signal quality even if everything is working. You can sometimes
head off future intermittent problems. The current generation of devices
draw such low power that they are more susceptible to noise than older
devices.

mikedunn

On 8/27/2010 4:00 AM, Samir Bendoukha wrote:
> *Adolf,*
>
> Thanks for the insight.
> *Jeff and Mike,
> *
> Sorry, I forgot to give more details. My board is very simple. I am using
> the C6747 to perform pulse detection and characterisation (using a dual
> channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
> some analogue outputs.
>
> - The TPS is sitting right next to the DSP and I am using the same design as
> in the OMAP137 EVM.
> - There is no external memory.
> - The DSP will be running at 300MHz, although I think it might be a bit
> excessive and might end up reducing it.
>
> Thanks for the help guys.
> Kind regards,
> Samir.
> On 26 August 2010 22:50, mikedunn wrote:
>
>> Samir,
>>
>> In addition to Jeff's comments...
>> The total make up of your board + 'what ever else might be on the 65023
>> input voltage and/or ground' is also important.
>> We do not know what you have - a simple board with just a DSP or a large 2
>> layer board with several banks of memory and some motor controllers [an
>> exageration to make a point].
>>
>> mikedunn
>> On 8/26/2010 11:48 AM, Jeff Brower wrote:
>>
>> Samir-
>>
>> You didn't mention which DSP, how fast it's running, how much memory (and
>> what kind). Wouldn't you think those things
>> are relevant to level of effort to ensure stability of core and IO
>> voltages?
>>
>> -Jeff
>>
>>> Just a couple of questions about power decoupling. I am using the
>> TPS65023
>>> to supply the 1.2V and 3.3V. The IC is very close to and solely supplies
>> the
>>> DSP. The datasheet mentions that one 100nF capacitor should be used per
>>> power pin. Since I am using the BGA package, this means the caps must be
>>> mounted on the bottom side of the PCB.
>>>
>>> Two questions:
>>>
>>> - I am I right in saying that the caps must be on the bottom side of the
>>> board? If so, it may be difficult for me.
>>> - Do I have to use all this capacitors? The application I am using the
>> DSP
>>> for is not that sensitive.
>>>
>>> --
>>> Kind regards,
>>> Samir.
>>>
>>> ---------------------------
>>> Samir Bendoukha
>>>
>>> "Computers are like air conditioners, they stop working properly if you
>> open
>>> Windows."
>>

_____________________________________ Start a New Thread

Samir-
> *Adolf,*
>
> Thanks for the insight.
>
> *Jeff and Mike,
> *
> Sorry, I forgot to give more details. My board is very simple. I am using
> the C6747 to perform pulse detection and characterisation (using a dual
> channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
> some analogue outputs.
>
> - The TPS is sitting right next to the DSP and I am using the same design as
> in the OMAP137 EVM

I have found the main priority is to treat the layout area for the switcher (TPS65023 in your case) as a small "sub-project" unto itself, and be as careful with that as you possibly can. Follow all TI
guidelines, use split ground planes (ask for schematic and layout review from a TI power FAE), try to keep all switcher-related traces on the same side as the TPS (for any that can't, run them on the nearest
gnd plane and etch out "banana" areas for those traces), and don't let any non-related signals in the switcher area. This goes a long way towards quiet Vcc core and IO levels.

The second thing is adequate bulk caps spread around the board and third is decoupling caps -- which is your question. Why can't you put decoupling caps on the back side under the DSP? What's your obstacle to
that? We're talking about 0402 size caps, not tall. If you can't follow TI guidelines (which may be overly cautious as Adolph and Mike have indicated) then place as many as possible. Typically pwr/gnd pin
placement on large BGA chips are designed by chipmakers such that you can obtain a basic "+" pattern on the back side -- suggest to try to achieve that if you can.
> - There is no external memory.
> - The DSP will be running at 300MHz, although I think it might be a bit
> excessive and might end up reducing it.

No external memory definitely makes quiet power easier, and slower DSP speed will always help. As Mike indicates, newer devices (e.g. C6747) == lower Vcc == higher sensitivity to power plane noise.

-Jeff
> On 26 August 2010 22:50, mikedunn wrote:
>
> > Samir,
> >
> > In addition to Jeff's comments...
> > The total make up of your board + 'what ever else might be on the 65023
> > input voltage and/or ground' is also important.
> > We do not know what you have - a simple board with just a DSP or a large 2
> > layer board with several banks of memory and some motor controllers [an
> > exageration to make a point].
> >
> > mikedunn
> >
> >
> > On 8/26/2010 11:48 AM, Jeff Brower wrote:
> >
> >
> >
> > Samir-
> >
> > You didn't mention which DSP, how fast it's running, how much memory (and
> > what kind). Wouldn't you think those things
> > are relevant to level of effort to ensure stability of core and IO
> > voltages?
> >
> > -Jeff
> >
> > > Just a couple of questions about power decoupling. I am using the
> > TPS65023
> > > to supply the 1.2V and 3.3V. The IC is very close to and solely supplies
> > the
> > > DSP. The datasheet mentions that one 100nF capacitor should be used per
> > > power pin. Since I am using the BGA package, this means the caps must be
> > > mounted on the bottom side of the PCB.
> > >
> > > Two questions:
> > >
> > > - I am I right in saying that the caps must be on the bottom side of the
> > > board? If so, it may be difficult for me.
> > > - Do I have to use all this capacitors? The application I am using the
> > DSP
> > > for is not that sensitive.
> > >
> > > --
> > > Kind regards,
> > > Samir.
> > >
> > > ---------------------------
> > > Samir Bendoukha
> > >
> > > "Computers are like air conditioners, they stop working properly if you
> > open
> > > Windows."
> > >
> >
> >
> >
> >
> > --
> Kind regards,
> Samir.
>
> ---------------------------
> Samir Bendoukha

_____________________________________ Start a New Thread

Samir-

> This might be a very stupid question but I am still new to PCB design (first
> every board!). How do I determine the ideal track width for my power, GND,
> and signals? I tried using the default technology file on easyPC, which
> gives 1.27, 1.27, and 0.38mm respectively. The tracks are huge compared to
> the QFN pins on the TPS65023!

Did you see the TPS65203 evaluation module? The docs for that should include layout info, an excellent reference for
you. What TI engineers do on their power device eval modules are like "golden examples" to follow, as they use the
eval modules for benchmarks, such as noise and ripple measurements.

-Jeff

> 2010/8/27 Jeff Brower > Samir-
>> > *Adolf,*
>> >
>> > Thanks for the insight.
>> >
>> > *Jeff and Mike,
>> > *
>> > Sorry, I forgot to give more details. My board is very simple. I am using
>> > the C6747 to perform pulse detection and characterisation (using a dual
>> > channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
>> > some analogue outputs.
>> >
>> > - The TPS is sitting right next to the DSP and I am using the same design
>> as
>> > in the OMAP137 EVM
>>
>> I have found the main priority is to treat the layout area for the switcher
>> (TPS65023 in your case) as a small "sub-project" unto itself, and be as
>> careful with that as you possibly can. Follow all TI
>> guidelines, use split ground planes (ask for schematic and layout review
>> from a TI power FAE), try to keep all switcher-related traces on the same
>> side as the TPS (for any that can't, run them on the nearest
>> gnd plane and etch out "banana" areas for those traces), and don't let any
>> non-related signals in the switcher area. This goes a long way towards
>> quiet Vcc core and IO levels.
>>
>> The second thing is adequate bulk caps spread around the board and third is
>> decoupling caps -- which is your question. Why can't you put decoupling
>> caps on the back side under the DSP? What's your obstacle to
>> that? We're talking about 0402 size caps, not tall. If you can't follow
>> TI guidelines (which may be overly cautious as Adolph and Mike have
>> indicated) then place as many as possible. Typically pwr/gnd pin
>> placement on large BGA chips are designed by chipmakers such that you can
>> obtain a basic "+" pattern on the back side -- suggest to try to achieve
>> that if you can.
>> > - There is no external memory.
>> > - The DSP will be running at 300MHz, although I think it might be a bit
>> > excessive and might end up reducing it.
>>
>> No external memory definitely makes quiet power easier, and slower DSP
>> speed will always help. As Mike indicates, newer devices (e.g. C6747) =>> lower Vcc == higher sensitivity to power plane noise.
>>
>> -Jeff
>> > On 26 August 2010 22:50, mikedunn wrote:
>> >
>> > > Samir,
>> > >
>> > > In addition to Jeff's comments...
>> > > The total make up of your board + 'what ever else might be on the 65023
>> > > input voltage and/or ground' is also important.
>> > > We do not know what you have - a simple board with just a DSP or a
>> large 2
>> > > layer board with several banks of memory and some motor controllers [an
>> > > exageration to make a point].
>> > >
>> > > mikedunn
>> > >
>> > >
>> > > On 8/26/2010 11:48 AM, Jeff Brower wrote:
>> > >
>> > >
>> > >
>> > > Samir-
>> > >
>> > > You didn't mention which DSP, how fast it's running, how much memory
>> (and
>> > > what kind). Wouldn't you think those things
>> > > are relevant to level of effort to ensure stability of core and IO
>> > > voltages?
>> > >
>> > > -Jeff
>> > >
>> > > > Just a couple of questions about power decoupling. I am using the
>> > > TPS65023
>> > > > to supply the 1.2V and 3.3V. The IC is very close to and solely
>> supplies
>> > > the
>> > > > DSP. The datasheet mentions that one 100nF capacitor should be used
>> per
>> > > > power pin. Since I am using the BGA package, this means the caps must
>> be
>> > > > mounted on the bottom side of the PCB.
>> > > >
>> > > > Two questions:
>> > > >
>> > > > - I am I right in saying that the caps must be on the bottom side of
>> the
>> > > > board? If so, it may be difficult for me.
>> > > > - Do I have to use all this capacitors? The application I am using
>> the
>> > > DSP
>> > > > for is not that sensitive.
>> > > >
>> > > > --
>> > > > Kind regards,
>> > > > Samir.
>> > > >
>> > > > ---------------------------
>> > > > Samir Bendoukha

_____________________________________ Start a New Thread

Hi,

This might be a very stupid question but I am still new to PCB design (first
every board!). How do I determine the ideal track width for my power, GND,
and signals? I tried using the default technology file on easyPC, which
gives 1.27, 1.27, and 0.38mm respectively. The tracks are huge compared to
the QFN pins on the TPS65023!

Am I missing somthing here?

Kind regards,
Samir.

2010/8/27 Jeff Brower

> Samir-
> > *Adolf,*
> >
> > Thanks for the insight.
> >
> > *Jeff and Mike,
> > *
> > Sorry, I forgot to give more details. My board is very simple. I am using
> > the C6747 to perform pulse detection and characterisation (using a dual
> > channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
> > some analogue outputs.
> >
> > - The TPS is sitting right next to the DSP and I am using the same design
> as
> > in the OMAP137 EVM
>
> I have found the main priority is to treat the layout area for the switcher
> (TPS65023 in your case) as a small "sub-project" unto itself, and be as
> careful with that as you possibly can. Follow all TI
> guidelines, use split ground planes (ask for schematic and layout review
> from a TI power FAE), try to keep all switcher-related traces on the same
> side as the TPS (for any that can't, run them on the nearest
> gnd plane and etch out "banana" areas for those traces), and don't let any
> non-related signals in the switcher area. This goes a long way towards
> quiet Vcc core and IO levels.
>
> The second thing is adequate bulk caps spread around the board and third is
> decoupling caps -- which is your question. Why can't you put decoupling
> caps on the back side under the DSP? What's your obstacle to
> that? We're talking about 0402 size caps, not tall. If you can't follow
> TI guidelines (which may be overly cautious as Adolph and Mike have
> indicated) then place as many as possible. Typically pwr/gnd pin
> placement on large BGA chips are designed by chipmakers such that you can
> obtain a basic "+" pattern on the back side -- suggest to try to achieve
> that if you can.
> > - There is no external memory.
> > - The DSP will be running at 300MHz, although I think it might be a bit
> > excessive and might end up reducing it.
>
> No external memory definitely makes quiet power easier, and slower DSP
> speed will always help. As Mike indicates, newer devices (e.g. C6747) => lower Vcc == higher sensitivity to power plane noise.
>
> -Jeff
> > On 26 August 2010 22:50, mikedunn wrote:
> >
> > > Samir,
> > >
> > > In addition to Jeff's comments...
> > > The total make up of your board + 'what ever else might be on the 65023
> > > input voltage and/or ground' is also important.
> > > We do not know what you have - a simple board with just a DSP or a
> large 2
> > > layer board with several banks of memory and some motor controllers [an
> > > exageration to make a point].
> > >
> > > mikedunn
> > >
> > >
> > > On 8/26/2010 11:48 AM, Jeff Brower wrote:
> > >
> > >
> > >
> > > Samir-
> > >
> > > You didn't mention which DSP, how fast it's running, how much memory
> (and
> > > what kind). Wouldn't you think those things
> > > are relevant to level of effort to ensure stability of core and IO
> > > voltages?
> > >
> > > -Jeff
> > >
> > > > Just a couple of questions about power decoupling. I am using the
> > > TPS65023
> > > > to supply the 1.2V and 3.3V. The IC is very close to and solely
> supplies
> > > the
> > > > DSP. The datasheet mentions that one 100nF capacitor should be used
> per
> > > > power pin. Since I am using the BGA package, this means the caps must
> be
> > > > mounted on the bottom side of the PCB.
> > > >
> > > > Two questions:
> > > >
> > > > - I am I right in saying that the caps must be on the bottom side of
> the
> > > > board? If so, it may be difficult for me.
> > > > - Do I have to use all this capacitors? The application I am using
> the
> > > DSP
> > > > for is not that sensitive.
> > > >
> > > > --
> > > > Kind regards,
> > > > Samir.
> > > >
> > > > ---------------------------
> > > > Samir Bendoukha
> > > >
> > > > "Computers are like air conditioners, they stop working properly if
> you
> > > open
> > > > Windows."
> > > >
> > >
> > >
> > >
> > >
> > >
> >
> > --
> > Kind regards,
> > Samir.
> >
> > ---------------------------
> > Samir Bendoukha
--
Kind regards,
Samir.

---------------------------
Samir Bendoukha

"Computers are like air conditioners, they stop working properly if you open
Windows." Start a New Thread

Samir,

these standard settings are certainly not adequate for a BGA and QFN
design! You will need much smaller trace and via structures, e.g. 4mil
(0.1-0.12mm) trace width and 25mil (0.4-0.5mm) vias to route signals inside
the BGA footprint. There are plenty of documents about BGA PCB layout on
the web, e.g. Texas Instruments SPRA429B, Fairchild AN-5026.
Also highly recommended: almost all evaluation board documentation contains
pcb prints. Use these as a starting point for your design.

For power tracks use a small width to connect to the package pin, then
widen the track as far as possible.

Best Regards,
Adolf Klemenz
At 13:38 01.09.2010 +0100, Samir Bendoukha wrote:
>Hi,
>
>This might be a very stupid question but I am still new to PCB design
>(first every board!). How do I determine the ideal track width for my
>power, GND, and signals? I tried using the default technology file on
>easyPC, which gives 1.27, 1.27, and 0.38mm respectively. The tracks are
>huge compared to the QFN pins on the TPS65023!
>
>Am I missing somthing here?
>
>Kind regards,
>Samir.
>
>2010/8/27 Jeff Brower <j...@signalogic.com>
>>Samir-
>> > *Adolf,*
>> >
>> > Thanks for the insight.
>> >
>> > *Jeff and Mike,
>> > *
>> > Sorry, I forgot to give more details. My board is very simple. I am using
>> > the C6747 to perform pulse detection and characterisation (using a dual
>> > channel SPI-ADC), VCO tuning, RS232/485 comms, an SPI, a JTAG, LEDs, and
>> > some analogue outputs.
>> >
>> > - The TPS is sitting right next to the DSP and I am using the same
>> design as
>> > in the OMAP137 EVM
>>
>>I have found the main priority is to treat the layout area for the
>>switcher (TPS65023 in your case) as a small "sub-project" unto itself,
>>and be as careful with that as you possibly can. Follow all TI
>>guidelines, use split ground planes (ask for schematic and layout review
>>from a TI power FAE), try to keep all switcher-related traces on the same
>>side as the TPS (for any that can't, run them on the nearest
>>gnd plane and etch out "banana" areas for those traces), and don't let
>>any non-related signals in the switcher area. This goes a long way
>>towards quiet Vcc core and IO levels.
>>
>>The second thing is adequate bulk caps spread around the board and third
>>is decoupling caps -- which is your question. Why can't you put
>>decoupling caps on the back side under the DSP? What's your obstacle to
>>that? We're talking about 0402 size caps, not tall. If you can't follow
>>TI guidelines (which may be overly cautious as Adolph and Mike have
>>indicated) then place as many as possible. Typically pwr/gnd pin
>>placement on large BGA chips are designed by chipmakers such that you can
>>obtain a basic "+" pattern on the back side -- suggest to try to achieve
>>that if you can.
>> > - There is no external memory.
>> > - The DSP will be running at 300MHz, although I think it might be a bit
>> > excessive and might end up reducing it.
>>
>>No external memory definitely makes quiet power easier, and slower DSP
>>speed will always help. As Mike indicates, newer devices (e.g. C6747) =>>lower Vcc == higher sensitivity to power plane noise.
>>
>>-Jeff
>> > On 26 August 2010 22:50, mikedunn
>> <m...@gmail.com> wrote:
>> >
>> > > Samir,
>> > >
>> > > In addition to Jeff's comments...
>> > > The total make up of your board + 'what ever else might be on the 65023
>> > > input voltage and/or ground' is also important.
>> > > We do not know what you have - a simple board with just a DSP or a
>> large 2
>> > > layer board with several banks of memory and some motor controllers [an
>> > > exageration to make a point].
>> > >
>> > > mikedunn
>> > >
>> > >
>> > > On 8/26/2010 11:48 AM, Jeff Brower wrote:
>> > >
>> > >
>> > >
>> > > Samir-
>> > >
>> > > You didn't mention which DSP, how fast it's running, how much memory
>> (and
>> > > what kind). Wouldn't you think those things
>> > > are relevant to level of effort to ensure stability of core and IO
>> > > voltages?
>> > >
>> > > -Jeff
>> > >
>> > > > Just a couple of questions about power decoupling. I am using the
>> > > TPS65023
>> > > > to supply the 1.2V and 3.3V. The IC is very close to and solely
>> supplies
>> > > the
>> > > > DSP. The datasheet mentions that one 100nF capacitor should be
>> used per
>> > > > power pin. Since I am using the BGA package, this means the caps
>> must be
>> > > > mounted on the bottom side of the PCB.
>> > > >
>> > > > Two questions:
>> > > >
>> > > > - I am I right in saying that the caps must be on the bottom side
>> of the
>> > > > board? If so, it may be difficult for me.
>> > > > - Do I have to use all this capacitors? The application I am using the
>> > > DSP
>> > > > for is not that sensitive.
>> > > >
>> > > > --
>> > > > Kind regards,
>> > > > Samir.
>> > > >
>> > > > ---------------------------
>> > > > Samir Bendoukha
>> > > >
>> > > > "Computers are like air conditioners, they stop working properly
>> if you
>> > > open
>> > > > Windows."
>> > > >
>> > >
>> > >
>> > >
>> > >
>> > >
>> >
>> > --
>> > Kind regards,
>> > Samir.
>> >
>> > ---------------------------
>> > Samir Bendoukha
>
>--
>Kind regards,
>Samir.
>
>---------------------------
>Samir Bendoukha
>
>"Computers are like air conditioners, they stop working properly if you
>open Windows."
>

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