parallel signal from adc to tms320c6455 dsk

Hello everybody,

I'm new to the group and to the whole field of DSPs, so I hope you'll be patient enough to read through my posts, correct any error and/or inaccuracy, and hopefully provide some answers that can help me advance in the understanding of this field of application.

Let's get to the point: I have to connect an A/D converter (AD9461) to a TMS320C6455 DSK board. The A/D converter provides a 16-bit parallel signal. There are three 80-pin connectors on the board: the memory expansion connector, the peripheral connector and the HPI/PCI connector.
At first I thought I could use the HPI connector, but then I found out the host to be connected must function as master and I don't think the A/D converter alone can function as master; moreover, the converter has to be synchronous with the DSP, using the clock of the latter.
So there remain the memory connector and the peripheral connector.
About the memory connector: could it be possible to use it to receive the parallel signal (kind of periodically reading from a memory location)?
About the peripheral connector: based on a quick reading of the documentation I know that this connector puts the signal on the McBSP bus, which requie serial signals, so a parallel to serial conversion is needed.

Based on the (superficial) understanding of the problem I have right now:
-is there anything I'm missing?
-what could be a convenient solution to connect those two devices?

Many thanks in advance for your answers.

_____________________________________ Start a New Thread

Hello,

I had to do similar problem as yourself for my thesis. I end up using the EMIF interface myself. I used the same DSK btw. So here are the couple of choices:

- Use FPGA or CPLD or micro-controller to create an interface between ADC and the HPI port. Max HPI frequency is 66 MHz I think, so this what can be done.

- EMIF port is indeed better. I used EMIF in asynchronous configuration. Without any board modifications (such as re-soldering the resistor) maximum memory transfer speed is 19.2 MHz (96 MHz ECLKOUT/5). If you re-solder resistor you you can get 30 MHz ADC clock. For any faster clock you need to have some kind of additional circuitry, such as again CPLD/FPGA. In either case EDMA will need to be set up to take care of it.

- Finally using McBSP is not a good idea I think. It's max speed is like 33 MHz I think and that's serial bus. So if you have 16-bit ADC then max speed you can achieve is like 2 MHz? And you need additional circuitry as well.

So based on these choices decide what is best.

Vladimir

--- In c..., cloneofmyself@... wrote:
>
> Hello everybody,
>
> I'm new to the group and to the whole field of DSPs, so I hope you'll be patient enough to read through my posts, correct any error and/or inaccuracy, and hopefully provide some answers that can help me advance in the understanding of this field of application.
>
> Let's get to the point: I have to connect an A/D converter (AD9461) to a TMS320C6455 DSK board. The A/D converter provides a 16-bit parallel signal. There are three 80-pin connectors on the board: the memory expansion connector, the peripheral connector and the HPI/PCI connector.
> At first I thought I could use the HPI connector, but then I found out the host to be connected must function as master and I don't think the A/D converter alone can function as master; moreover, the converter has to be synchronous with the DSP, using the clock of the latter.
> So there remain the memory connector and the peripheral connector.
> About the memory connector: could it be possible to use it to receive the parallel signal (kind of periodically reading from a memory location)?
> About the peripheral connector: based on a quick reading of the documentation I know that this connector puts the signal on the McBSP bus, which requie serial signals, so a parallel to serial conversion is needed.
>
> Based on the (superficial) understanding of the problem I have right now:
> -is there anything I'm missing?
> -what could be a convenient solution to connect those two devices?
>
> Many thanks in advance for your answers.
>

_____________________________________ Start a New Thread

Vladimir

Excellent post... sounds like you got your thesis project working. Your Prof must have been impressed.

> I had to do similar problem as yourself for my thesis. I end up using the EMIF interface myself. I used the same DSK
> btw. So here are the couple of choices:
>
> - Use FPGA or CPLD or micro-controller to create an interface between ADC and the HPI port. Max HPI frequency is 66
> MHz I think, so this what can be done.
>
> - EMIF port is indeed better. I used EMIF in asynchronous configuration. Without any board modifications (such as
> re-soldering the resistor) maximum memory transfer speed is 19.2 MHz (96 MHz ECLKOUT/5). If you re-solder resistor you
> you can get 30 MHz ADC clock. For any faster clock you need to have some kind of additional circuitry, such as again
> CPLD/FPGA. In either case EDMA will need to be set up to take care of it.

I have a question: when you say additional circuitry would be needed for 30 MHz ADC rate, is that only to supply the
clock or (also) because the daughtercard interface has EMIF signal integrity problems at higher rates?

-Jeff

> - Finally using McBSP is not a good idea I think. It's max speed is like 33 MHz I think and that's serial bus. So if
> you have 16-bit ADC then max speed you can achieve is like 2 MHz? And you need additional circuitry as well.
>
> So based on these choices decide what is best.
>
> Vladimir
>
> --- In c..., cloneofmyself@... wrote:
>>
>> Hello everybody,
>>
>> I'm new to the group and to the whole field of DSPs, so I hope you'll be patient enough to read through my posts,
>> correct any error and/or inaccuracy, and hopefully provide some answers that can help me advance in the
>> understanding of this field of application.
>>
>> Let's get to the point: I have to connect an A/D converter (AD9461) to a TMS320C6455 DSK board. The A/D converter
>> provides a 16-bit parallel signal. There are three 80-pin connectors on the board: the memory expansion connector,
>> the peripheral connector and the HPI/PCI connector.
>> At first I thought I could use the HPI connector, but then I found out the host to be connected must function as
>> master and I don't think the A/D converter alone can function as master; moreover, the converter has to be
>> synchronous with the DSP, using the clock of the latter.
>> So there remain the memory connector and the peripheral connector.
>> About the memory connector: could it be possible to use it to receive the parallel signal (kind of periodically
>> reading from a memory location)?
>> About the peripheral connector: based on a quick reading of the documentation I know that this connector puts the
>> signal on the McBSP bus, which requie serial signals, so a parallel to serial conversion is needed.
>>
>> Based on the (superficial) understanding of the problem I have right now:
>> -is there anything I'm missing?
>> -what could be a convenient solution to connect those two devices?
>>
>> Many thanks in advance for your answers.

_____________________________________ Start a New Thread

Vladimir,

thank you so much for your answer. I'll try to put your suggestions to good use.

Lee-Mort_Atchi

_____________________________________ Start a New Thread

Jeff and Lee-Mort,

First of all to answer your question Jeff: according to the 6455 DSK manual EMIF connector only provides asynchronous access. I am not quite sure of that, but if this is indeed true, the fastest clock you can get is when HOLD = STROBE = SETUP = 1 ECLKOUT, and then there is a minimum turn around time of 2 ECLKOUTs. Therefore with the max ECLCKOUT of 150 MHz, you can get only 30 MHz asynchronous memory clock. If synchronous memory can be used, despite what manual says, then max clock can be up to 166 MHz.

Also, I made an error when I made a post. I made EMIF to DAC connection, not the EMIF to ADC. I have connected the ADC to the HPI port using an FPGA as pre-processing and control module. I think that ADC to EMIF is still easier to do and will not require anything extra. First of all, I have seen application notes and projects online that talk about EMIF to ADC connection. Second, drawback of EMIF is that it does not have an event that can be used by EDMA. Therefore, a timer event needs to be used to transfer ADC readings into the memory via EDMA. It is important to make sure timer events and the memory writes, are synchronized. Another option is to connect clock from memory writes, to the GPIO pin, and use that as the EDMA event.

Hope this adds a little more help. Also I am going to see if I can post some of my thesis and code work.

Vladimir

_____________________________________ Start a New Thread

I'm a little late coming into this thread. We have done exactly what you
describe below. Since one of the ADC signals is a WORD (or left right) clock in
our case, we used that (via GPIO) to trigger an EDMA event. Seems you are on
that track anyway. I'm just confirming that it can definitely work.

- Andrew

________________________________
From: vterrap
To: c...
Sent: Mon, April 25, 2011 10:10:20 AM
Subject: [c6x] Re: parallel signal from adc to tms320c6455 dsk

Jeff and Lee-Mort,

First of all to answer your question Jeff: according to the 6455 DSK manual EMIF
connector only provides asynchronous access. I am not quite sure of that, but if
this is indeed true, the fastest clock you can get is when HOLD = STROBE = SETUP
= 1 ECLKOUT, and then there is a minimum turn around time of 2 ECLKOUTs.
Therefore with the max ECLCKOUT of 150 MHz, you can get only 30 MHz asynchronous
memory clock. If synchronous memory can be used, despite what manual says, then
max clock can be up to 166 MHz.

Also, I made an error when I made a post. I made EMIF to DAC connection, not the
EMIF to ADC. I have connected the ADC to the HPI port using an FPGA as
pre-processing and control module. I think that ADC to EMIF is still easier to
do and will not require anything extra. First of all, I have seen application
notes and projects online that talk about EMIF to ADC connection. Second,
drawback of EMIF is that it does not have an event that can be used by EDMA.
Therefore, a timer event needs to be used to transfer ADC readings into the
memory via EDMA. It is important to make sure timer events and the memory
writes, are synchronized. Another option is to connect clock from memory writes,
to the GPIO pin, and use that as the EDMA event.

Hope this adds a little more help. Also I am going to see if I can post some of
my thesis and code work.

Vladimir Start a New Thread

Vladimir-

> First of all to answer your question Jeff: according to
> the 6455 DSK manual EMIF connector only provides asynchronous
> access. I am not quite sure of that, but if this is
> indeed true, the fastest clock you can get is when HOLD = STROBE > SETUP = 1 ECLKOUT, and then there is a minimum turn
> around time of 2 ECLKOUTs. Therefore with the max
> ECLCKOUT of 150 MHz, you can get only 30 MHz
> asynchronous memory clock.

Thanks for this info. But... that should not be the case. Typical fast SRAM access is 8 to 10 nsec, so at least 100
MHz clock should be possible. DSPs have been capable of 100+ MHz async mem rates for 12+ years, including 54x, 55x,
and 64x series, so I can't imagine the DSK 6455 is any slower.

> If synchronous memory can be used, despite what manual says,
> then max clock can be up to 166 MHz.
>
> Also, I made an error when I made a post. I made EMIF to DAC connection, not the EMIF to ADC. I have connected the ADC
> to the HPI port using an FPGA as pre-processing and control module. I think that ADC to EMIF is still easier to do and
> will not require anything extra. First of all, I have seen application notes and projects online that talk about EMIF
> to ADC connection. Second, drawback of EMIF is that it does not have an event that can be used by EDMA. Therefore, a
> timer event needs to be used to transfer ADC readings into the memory via EDMA. It is important to make sure timer
> events and the memory writes, are synchronized. Another option is to connect clock from memory writes, to the GPIO
> pin, and use that as the EDMA event.

At a 30 MHz rate, GPIO should work. For fast rates (say, HD video at 30 fps), if the ADC had a FIFO -- or one was
added to the daughtercard circuitry -- then it might be reasonable to rely on cache controller EDMA transfers. In
that case the event would be a "FIFO full" (or half-full) signal to an external interrupt.

-Jeff

_____________________________________ Start a New Thread

Vladimir,

My expectation is a ADC would have a 'conversion complete' signal output.
That signal can be routed to a GPIO input and used to trigger an interrupt.
The DMA/EDMA can be set to work with that interrupt.
The ADC will also need a signal to start the next conversion.
When the above is completed, the ADC can be read at its' full speed.

R. Williams

---------- Original Message -----------
From: "Jeff Brower"
To: c...
Cc: "Vladimir"
Sent: Mon, 25 Apr 2011 16:13:56 -0500 (CDT)
Subject: Re: [c6x] Re: parallel signal from adc to tms320c6455 dsk

> Vladimir-
>
> > First of all to answer your question Jeff: according to
> > the 6455 DSK manual EMIF connector only provides asynchronous
> > access. I am not quite sure of that, but if this is
> > indeed true, the fastest clock you can get is when HOLD = STROBE > > SETUP = 1 ECLKOUT, and then there is a minimum turn
> > around time of 2 ECLKOUTs. Therefore with the max
> > ECLCKOUT of 150 MHz, you can get only 30 MHz
> > asynchronous memory clock.
>
> Thanks for this info. But... that should not be the case. Typical
> fast SRAM access is 8 to 10 nsec, so at least 100 MHz clock should be
> possible. DSPs have been capable of 100+ MHz async mem rates for 12+
> years, including 54x, 55x, and 64x series, so I can't imagine the DSK
> 6455 is any slower.
>
> > If synchronous memory can be used, despite what manual says,
> > then max clock can be up to 166 MHz.
> >
> > Also, I made an error when I made a post. I made EMIF to DAC connection, not
the EMIF to ADC. I have connected the ADC
> > to the HPI port using an FPGA as pre-processing and control module. I think
that ADC to EMIF is still easier to do and
> > will not require anything extra. First of all, I have seen application notes
and projects online that talk about EMIF
> > to ADC connection. Second, drawback of EMIF is that it does not have an
event that can be used by EDMA. Therefore, a
> > timer event needs to be used to transfer ADC readings into the memory via
EDMA. It is important to make sure timer
> > events and the memory writes, are synchronized. Another option is to connect
clock from memory writes, to the GPIO
> > pin, and use that as the EDMA event.
>
> At a 30 MHz rate, GPIO should work. For fast rates (say, HD video at
> 30 fps), if the ADC had a FIFO -- or one was added to the daughtercard
> circuitry -- then it might be reasonable to rely on cache controller
> EDMA transfers. In that case the event would be a "FIFO full" (or
> half-full) signal to an external interrupt.
>
> -Jeff
------- End of Original Message -------

_____________________________________ Start a New Thread

Vladimir,

On 4/25/2011 9:10 AM, vterrap wrote:
>
> Jeff and Lee-Mort,
>
> First of all to answer your question Jeff: according to the 6455 DSK
> manual EMIF connector only provides asynchronous access. I am not
> quite sure of that, but if this is indeed true, the fastest clock you
> can get is when HOLD = STROBE = SETUP = 1 ECLKOUT, and then there is a
> minimum turn around time of 2 ECLKOUTs. Therefore with the max
> ECLCKOUT of 150 MHz, you can get only 30 MHz asynchronous memory
> clock. If synchronous memory can be used, despite what manual says,
> then max clock can be up to 166 MHz.
>

FYI-The "synchronous memory cannot be used" is a half truth. Synchronous
Dynamic RAMs cannot be used - I'm not sure if you misread it or it was
printed wrong.
I don't know the specifics of the 6455 EMIF external logic and board
layout, but I would expect it to support SRAMs at 90-133 Mhz.

mikedunn
> Also, I made an error when I made a post. I made EMIF to DAC
> connection, not the EMIF to ADC. I have connected the ADC to the HPI
> port using an FPGA as pre-processing and control module. I think that
> ADC to EMIF is still easier to do and will not require anything extra.
> First of all, I have seen application notes and projects online that
> talk about EMIF to ADC connection. Second, drawback of EMIF is that it
> does not have an event that can be used by EDMA. Therefore, a timer
> event needs to be used to transfer ADC readings into the memory via
> EDMA. It is important to make sure timer events and the memory writes,
> are synchronized. Another option is to connect clock from memory
> writes, to the GPIO pin, and use that as the EDMA event.
>
> Hope this adds a little more help. Also I am going to see if I can
> post some of my thesis and code work.
>
> Vladimir Start a New Thread

Mike,

You are right. DSK reference said that it has asynchronous outputs only. I suppose synchronous memory can still be implemented as ECLKOUT output is present. Also I was referring to DSK, not to the C6455 by itself.

Vladimir

--- In c..., mikedunn wrote:
>
> Vladimir,
>
> On 4/25/2011 9:10 AM, vterrap wrote:
> >
> > Jeff and Lee-Mort,
> >
> > First of all to answer your question Jeff: according to the 6455 DSK
> > manual EMIF connector only provides asynchronous access. I am not
> > quite sure of that, but if this is indeed true, the fastest clock you
> > can get is when HOLD = STROBE = SETUP = 1 ECLKOUT, and then there is a
> > minimum turn around time of 2 ECLKOUTs. Therefore with the max
> > ECLCKOUT of 150 MHz, you can get only 30 MHz asynchronous memory
> > clock. If synchronous memory can be used, despite what manual says,
> > then max clock can be up to 166 MHz.
> >
>
> FYI-The "synchronous memory cannot be used" is a half truth. Synchronous
> Dynamic RAMs cannot be used - I'm not sure if you misread it or it was
> printed wrong.
> I don't know the specifics of the 6455 EMIF external logic and board
> layout, but I would expect it to support SRAMs at 90-133 Mhz.
>
> mikedunn
> >
> >
> > Also, I made an error when I made a post. I made EMIF to DAC
> > connection, not the EMIF to ADC. I have connected the ADC to the HPI
> > port using an FPGA as pre-processing and control module. I think that
> > ADC to EMIF is still easier to do and will not require anything extra.
> > First of all, I have seen application notes and projects online that
> > talk about EMIF to ADC connection. Second, drawback of EMIF is that it
> > does not have an event that can be used by EDMA. Therefore, a timer
> > event needs to be used to transfer ADC readings into the memory via
> > EDMA. It is important to make sure timer events and the memory writes,
> > are synchronized. Another option is to connect clock from memory
> > writes, to the GPIO pin, and use that as the EDMA event.
> >
> > Hope this adds a little more help. Also I am going to see if I can
> > post some of my thesis and code work.
> >
> > Vladimir
> >
>

_____________________________________ Start a New Thread