EDMA 1-D data transfer issue in C6713

Hi,

In my design, the McASP is connected to a 6-channel ADC through a McASP.

I have configured the McASP in synchronous TDM mode and wanted to configure

EDMA to transfer the data received from the McASP port to a variable in CE0
space.

The CE0 space is connected to a FPGA. And there is code in FPGA which takes
the EMIF signals

and acts as a asynchronous SRAM.

This is how I have configured my EDMA port.

/* Configure EDMA parameters */

EDMA_configArgs(
hEdmaAREVT,
EDMA_OPT_RMK(
EDMA_OPT_PRI_HIGH,
EDMA_OPT_ESIZE_16BIT, /* Element size 32 bits */
EDMA_OPT_2DS_NO,
EDMA_OPT_SUM_NONE,
EDMA_OPT_2DD_NO,
EDMA_OPT_DUM_INC,
EDMA_OPT_TCINT_YES, /* Enable Transfer Complete
Interrupt */
EDMA_OPT_TCC_OF(edmaChaAREVT),
EDMA_OPT_LINK_NO, /* Enable linking to NULL
table */
EDMA_OPT_FS_YES
),
EDMA_SRC_RMK(MCASP_getRbufAddr(hMcasp)),
EDMA_CNT_OF(0x00000006),/* no. of elements */
EDMA_DST_RMK((int32_t)RxData),
EDMA_IDX_OF(0x00000000),
EDMA_RLD_OF(0x00060000)
);

/* Enable EDMA interrupts */
EDMA_intDisable(edmaChaAREVT);
EDMA_intClear(edmaChaAREVT);
EDMA_intEnable(edmaChaAREVT);

/* enable EDMA channels */
EDMA_enableChannel(hEdmaAREVT);

The main aim is to transfer the 6 TDM data words from the McASP to the CE0
locations continuously.

But in the CE0 space, I am able to receive all the 6 data words at same
address "0. while I want to receive the data in contiguous

address locations (see parameter INC in OPT register, DUM bit).

Could somebody please suggest if there is something I am missing in the EDMA
configuration. Please guide.

Thanks,

Aditi. Start a New Thread

Varoonian,

I am seding in a 48MHz clock to ECLKIN.
And ECLKSRC in DEVCFG register is set to be ECLKIN.

Any other place to look at.

Thanks,
Aditi.

On Tue, Jun 21, 2011 at 11:00 PM, varoonian . wrote:

> Aditi,
>
> I think your code looks alright. I have a question for you.
>
> What did your EMIF clock look like ? Did you run it at 125 MHz ? If not,
> how do you lower the frequency of operation of the EMIF.
>
> Thanks,
>
> On Tue, Jun 21, 2011 at 10:13 AM, Aditi Akula wrote:
>
>> **
>> Hi,
>>
>> In my design, the McASP is connected to a 6-channel ADC through a McASP.
>>
>> I have configured the McASP in synchronous TDM mode and wanted to
>> configure
>>
>> EDMA to transfer the data received from the McASP port to a variable in
>> CE0 space.
>>
>> The CE0 space is connected to a FPGA. And there is code in FPGA which
>> takes the EMIF signals
>>
>> and acts as a asynchronous SRAM.
>>
>> This is how I have configured my EDMA port.
>>
>> /* Configure EDMA parameters */
>>
>> EDMA_configArgs(
>> hEdmaAREVT,
>> EDMA_OPT_RMK(
>> EDMA_OPT_PRI_HIGH,
>> EDMA_OPT_ESIZE_16BIT, /* Element size 32 bits */
>> EDMA_OPT_2DS_NO,
>> EDMA_OPT_SUM_NONE,
>> EDMA_OPT_2DD_NO,
>> EDMA_OPT_DUM_INC,
>> EDMA_OPT_TCINT_YES, /* Enable Transfer Complete
>> Interrupt */
>> EDMA_OPT_TCC_OF(edmaChaAREVT),
>> EDMA_OPT_LINK_NO, /* Enable linking to NULL
>> table */
>> EDMA_OPT_FS_YES
>> ),
>> EDMA_SRC_RMK(MCASP_getRbufAddr(hMcasp)),
>> EDMA_CNT_OF(0x00000006),/* no. of elements */
>> EDMA_DST_RMK((int32_t)RxData),
>> EDMA_IDX_OF(0x00000000),
>> EDMA_RLD_OF(0x00060000)
>> );
>>
>> /* Enable EDMA interrupts */
>> EDMA_intDisable(edmaChaAREVT);
>> EDMA_intClear(edmaChaAREVT);
>> EDMA_intEnable(edmaChaAREVT);
>>
>> /* enable EDMA channels */
>> EDMA_enableChannel(hEdmaAREVT);
>>
>> The main aim is to transfer the 6 TDM data words from the McASP to the CE0
>> locations continuously.
>>
>> But in the CE0 space, I am able to receive all the 6 data words at same
>> address "0. while I want to receive the data in contiguous
>>
>> address locations (see parameter INC in OPT register, DUM bit).
>>
>> Could somebody please suggest if there is something I am missing in the
>> EDMA configuration. Please guide.
>>
>> Thanks,
>>
>> Aditi.
>>
>>
>> --
> Varun
> Start a New Thread