FIR filtering with differential design

Greetings,

I have to use a digital FIR filter on a transmitter side having root
raised cosine characteristic.

I understand we need to have one FIR on I channel and one FIR on Q
channel.

What is it going to be if I have differential I and Q, meaning I+, I-
and Q+, Q-.

Do we need to implement one filter on each single ended signal,
meaning a total of 4 filters?

Let me know if you have past experience on differential FIR filtering.

Thank you so much,
Patrick

On 01/28/2011 01:02 PM, fpgaasicdesigner wrote:
> Greetings,
>
> I have to use a digital FIR filter on a transmitter side having root
> raised cosine characteristic.
>
> I understand we need to have one FIR on I channel and one FIR on Q
> channel.
>
> What is it going to be if I have differential I and Q, meaning I+, I-
> and Q+, Q-.
>
> Do we need to implement one filter on each single ended signal,
> meaning a total of 4 filters?
>
> Let me know if you have past experience on differential FIR filtering.

Normally you would just calculate I = I+ - I-, ditto for Q.  Normally if 
you had differential voltages coming out of some chip, you'd feed them 
into a differential ADC and just get I and Q digitally.

Mathematically, taking the 'four FIR' approach and subtracting after the 
fact isn't any different than subtracting before hand and then doing two 
FIR filters -- but the number of computations is sure different.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Tim Wescott <tim@seemywebsite.com> wrote:
> On 01/28/2011 01:02 PM, fpgaasicdesigner wrote:

(snip)
>> I understand we need to have one FIR on I channel and one FIR on Q
>> channel.

>> What is it going to be if I have differential I and Q, meaning I+, I-
>> and Q+, Q-.

>> Do we need to implement one filter on each single ended signal,
>> meaning a total of 4 filters?

(snip) 
> Normally you would just calculate I = I+ - I-, ditto for Q.  Normally if 
> you had differential voltages coming out of some chip, you'd feed them 
> into a differential ADC and just get I and Q digitally.
 
> Mathematically, taking the 'four FIR' approach and subtracting after the 
> fact isn't any different than subtracting before hand and then doing two 
> FIR filters -- but the number of computations is sure different.

My first thought on that is that the input might be symmetric,
such that I+ = -I-, and so I would be even, but after filtering
it might not be even.  If you filter I/2, then use the output
and its inverse, that seems like it should work.

Otherwise, if the filter output is odd, then you have to decide
how to generate the differential outputs.  Or if the input is
not symmetric, maybe off by at most one, then the output
should also have that property.

-- glen

>Tim Wescott <tim@seemywebsite.com> wrote:
>> On 01/28/2011 01:02 PM, fpgaasicdesigner wrote:
>
>(snip)
>>> What is it going to be if I have differential I and Q, meaning I+, I-
>>> and Q+, Q-.
>
>(snip) 
>> Normally you would just calculate I = I+ - I-, ditto for Q.  Normally if

>> you had differential voltages coming out of some chip, you'd feed them 
>> into a differential ADC and just get I and Q digitally.
>
>My first thought on that is that the input might be symmetric,
>such that I+ = -I-, and so I would be even, but after filtering
>it might not be even.  If you filter I/2, then use the output
>and its inverse, that seems like it should work.

Normally, in the analog world, differential signaling is used to cancel out
common mode noise.  Thus, it is expected that I+ and I- are not perfectly
symmetrical.  The desired signal part is symmetrical and of opposite
polarity, but any noise is hopefully symmetrical and of the same polarity. 
When you combine I+ and I- via I = I+ - I-, then you end up canceling out
nearly all o the noise, but getting the original signal reinforced to +6
dB.  You can divide by 2, which restores the desired signal to 0 dB while
further reducing any remaining, non-common-mode noise by 6 dB.

In other words, you don't want to estimate I by calculating I+/2.  You want
to actually calculate I+ - I- and use that result, whether you divide by 2
or not depends upon your overall signal chain.


>Otherwise, if the filter output is odd, then you have to decide
>how to generate the differential outputs.  Or if the input is
>not symmetric, maybe off by at most one, then the output
>should also have that property.

I am not sure that I follow what you're saying here, but it sounds like
you're trying to generate differential output as well as process
differential input.  It doesn't quite make sense to generate differential
outputs in the digital domain, because it is assumed that digital
transmission is not susceptible to noise.  If you are converting to analog,
then differential would be useful, but most of the time a differential DAC
is used, and so your code would only deal with a single-ended signal.

I think that we need to know more about your overall system, otherwise
there's the risk that you're doing unnecessary calculations or perhaps
skipping steps that are needed.

Brian Willoughby
Sound Consulting

On Jan 28, 10:24&#4294967295;pm, Tim Wescott <t...@seemywebsite.com> wrote:
> On 01/28/2011 01:02 PM, fpgaasicdesigner wrote:
>
> > Greetings,
>
> > I have to use a digital FIR filter on a transmitter side having root
> > raised cosine characteristic.
>
> > I understand we need to have one FIR on I channel and one FIR on Q
> > channel.
>
> > What is it going to be if I have differential I and Q, meaning I+, I-
> > and Q+, Q-.
>
> > Do we need to implement one filter on each single ended signal,
> > meaning a total of 4 filters?

You *can* do that, but you don't *need* to.

> > Let me know if you have past experience on differential FIR filtering.
>
> Normally you would just calculate I = I+ - I-, ditto for Q. &#4294967295;Normally if
> you had differential voltages coming out of some chip, you'd feed them
> into a differential ADC and just get I and Q digitally.
>
> Mathematically, taking the 'four FIR' approach and subtracting after the
> fact isn't any different than subtracting before hand and then doing two
> FIR filters -- but the number of computations is sure different.

In a perfect world it's up to the system designer to decide where
to insert the filters. The fact that one is dealing with linear
systems ensures that the end result *formally* is the same,
regardless of the order of the sum or difference and the filter.

In *practice* there might be very good reasons to choose one
order or the other to do things:

1) One solution will require fewer flops than the other
2) One solution will exhibit better numerical properties
   due to finite precision arithmetics and roundoff errors,
   than the other

Usually, the solution that scores better from one perspective
is not the same that scores good from the other perspective:
Fast solutions often have poor numerical properties.

I have no idea what the analysis will turn up in this particular
case (the fast difference-then-filter solution may or may not also
have the better numerical properties), but questions like these
usually decide what practical method to use when several possible
choises are formally equivalent.

Rune

On 1/28/2011 4:43 PM, rsdio wrote:
>> Tim Wescott<tim@seemywebsite.com>  wrote:
>>> On 01/28/2011 01:02 PM, fpgaasicdesigner wrote:
>>
>> (snip)
>>>> What is it going to be if I have differential I and Q, meaning I+, I-
>>>> and Q+, Q-.
>>
>> (snip)
>>> Normally you would just calculate I = I+ - I-, ditto for Q.  Normally if
>
>>> you had differential voltages coming out of some chip, you'd feed them
>>> into a differential ADC and just get I and Q digitally.
>>
>> My first thought on that is that the input might be symmetric,
>> such that I+ = -I-, and so I would be even, but after filtering
>> it might not be even.  If you filter I/2, then use the output
>> and its inverse, that seems like it should work.
>
> Normally, in the analog world, differential signaling is used to cancel out
> common mode noise.  Thus, it is expected that I+ and I- are not perfectly
> symmetrical.  The desired signal part is symmetrical and of opposite
> polarity, but any noise is hopefully symmetrical and of the same polarity.
> When you combine I+ and I- via I = I+ - I-, then you end up canceling out
> nearly all o the noise, but getting the original signal reinforced to +6
> dB.  You can divide by 2, which restores the desired signal to 0 dB while
> further reducing any remaining, non-common-mode noise by 6 dB.
>
> In other words, you don't want to estimate I by calculating I+/2.  You want
> to actually calculate I+ - I- and use that result, whether you divide by 2
> or not depends upon your overall signal chain.
>
>
>> Otherwise, if the filter output is odd, then you have to decide
>> how to generate the differential outputs.  Or if the input is
>> not symmetric, maybe off by at most one, then the output
>> should also have that property.
>
> I am not sure that I follow what you're saying here, but it sounds like
> you're trying to generate differential output as well as process
> differential input.  It doesn't quite make sense to generate differential
> outputs in the digital domain, because it is assumed that digital
> transmission is not susceptible to noise.  If you are converting to analog,
> then differential would be useful, but most of the time a differential DAC
> is used, and so your code would only deal with a single-ended signal.
>
> I think that we need to know more about your overall system, otherwise
> there's the risk that you're doing unnecessary calculations or perhaps
> skipping steps that are needed.
>
> Brian Willoughby
> Sound Consulting

I agree.  Brian beat me to it!  :-) Or, are we missing something 
important that you haven't told us?

Fred