Hi, I am trying to implement a filterbank with IIR on Xilinx FPGA. Does anyone have experience on similar project? Right now, I am using direct form I second-order-series for the IIR. However, when I tried to generate the vhdl code in simulink, I was informed that the timing constraints could not be met. I think the problem might comes from the feedback loop in the IIR. Anyone could help? Thanks in advance, androm This message was sent using the Comp.DSP web interface on www.DSPRelated.com
Implementing IIR on Xilinx?
Started by ●August 30, 2005
Reply by ●August 30, 20052005-08-30
androm wrote:> Hi, I am trying to implement a filterbank with IIR on Xilinx FPGA. Does > anyone have experience on similar project? Right now, I am using direct > form I second-order-series for the IIR. However, when I tried to generate > the vhdl code in simulink, I was informed that the timing constraints could > not be met. I think the problem might comes from the feedback loop in the > IIR. Anyone could help? > > Thanks in advance, > androm >This is so heavily dependent on how you are implementing your multiplies, etc., that there isn't enough detail in your post. Does your IIR filter have to run at the clock rate of your FPGA? If not there may be opportunities to pipeline your arithmetic to meet timing. Where are you being told you won't meet timing? Surely Simulink is happily unaware of any timing issues -- I assume it's in your synthesizer? You may have to just take the VHDL generated by Simulink and hand-tune it for speed. You may, in fact, be able to find the DSP functions you need on your FPGA manufacturer's website and bypass Simulink-generated design altogether. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com