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Hi, My pm_data and dm_data are in the memory locations START(0x0000c000) END(0x0000cfff) and START(0x0000d000) END(0x0000dfff) respectively. I want to maximize my dm_data so I transferred my pm_data to START (0x00009400) END(0x00009fff) and my dm_data then becomes START (0x0000c000) END(0x0000dfff). There are no errors but when loading to the debugger VDSP++ 1.0 there is an error an invalid data from pm_data. How can I make this setup of my memory locations work? My second problem is with using the sdram. It is declared as a dm memory space. I used to access it like dm_data with DAGs. But my adviser told me that this is wrong because several data is passing thru the external bus and I don't know if the data I'm getting is actually from the sdram or some other data location. He says I should use DMA. How true is this? What instructions do I use? Can I use it in my delay line in an IIR form II implementation which has 3000 total taps @ 16khz? Tnx Ishmael |
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pm and dm data, sdram of ADSP 21065L EZ-KIT Lite
Started by ●July 19, 2002
Reply by ●July 20, 20022002-07-20
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[Please reply to the list.] On Thu, 2002-07-18 at 18:08, normal_ozone wrote: > My pm_data and dm_data are in the memory locations START(0x0000c000) > END(0x0000cfff) and START(0x0000d000) END(0x0000dfff) respectively. I > want to maximize my dm_data so I transferred my pm_data to START > (0x00009400) END(0x00009fff) and my dm_data then becomes START > (0x0000c000) END(0x0000dfff). > > There are no errors but when loading to the debugger VDSP++ 1.0 there > is an error an invalid data from pm_data. This sounds like an error I recall in the linker. Check with your supplier for access to a fixed version. > My second problem is with using the sdram. It is declared as a dm > memory space. I used to access it like dm_data with DAGs. But my > adviser told me that this is wrong because several data is passing > thru the external bus and I don't know if the data I'm getting is > actually from the sdram or some other data location. > > He says I should use DMA. Nope. External memory works like DM internal memory, and you can access it with DAG1 with no special work. You can also load and store with it directly. You can also execute code from external memory addressed by MS0, but (as with addressing of internal memory blocks) the instruction address will not match the physical bus address. > How true is this? What instructions do I use? Can I use it in my > delay line in an IIR form II implementation which has 3000 total taps > @ 16khz? Hard to say. Try using the simulator see what effect SDRAM timing would have on your throughput. SDRAM throughput benefits from sequential accesses. Random accesses will tend to be very slow because the time to first access is long, and only successive accesses to sequential locations will happen at the internal SHARC clock rate. |
