How to build variable-cutoff LPF with very high oversapling

Started by whee...@yahoo.com in DSP & FPGA4 years ago

Hello all, I'm using a Xilinx Kintex-7 FPGA to do some low-pass filtering using System Generator/Simulink, and had a question about the...

Hello all, I'm using a Xilinx Kintex-7 FPGA to do some low-pass filtering using System Generator/Simulink, and had a question about the architecture of the filter. My requirements include having to use a fixed sampling rate of 80MSPS. This can't really change. I appreciate the difference b/w sample rate of the filter and the clock rate of the DSP primitives in the FPGA. The customer wants...


What the difference between ARM and DSP core when accessing FPGA using EMIFA in omapl138?

Started by shiv...@gmail.com in DSP & FPGA4 years ago

Hi, I want to use EMIFA to access a dual port RAM in FPGA, which is designed to be 16-bit in width and 256-byte in depth. I have configured the...

Hi, I want to use EMIFA to access a dual port RAM in FPGA, which is designed to be 16-bit in width and 256-byte in depth. I have configured the EMIFA to be 16-bit data width, and used memcpy() to copy an array of the type of unsigned char into the dual port RAM. The ARM core can complete this course exactly, however, the DSP core can only complete it rigthly under an condition that the size of...


fft in verilog

Started by fren...@yahoo.com in DSP & FPGA4 years ago 4 replies

Hello I have some questions related to verilog. How can I create a N by N matrix in verilog? In Matlab u create the signal yourself. Is it the...

Hello I have some questions related to verilog. How can I create a N by N matrix in verilog? In Matlab u create the signal yourself. Is it the same in verilog? cause I have to implement the overlap-save method on a FPGA board (I don't know if you have heard of it). For this, I have a signal, I have to split it in blocks of the same size and for each block to compute the FFT. I want to create a ...


Basic Sampling Question

Started by mlip...@gmail.com in DSP & FPGA5 years ago 1 reply

I am new to DSP area and have a basic question about the Nyquist Theorem. Basically to sample a sine wave, for example, I need to sample at twice...

I am new to DSP area and have a basic question about the Nyquist Theorem. Basically to sample a sine wave, for example, I need to sample at twice the frequency of the signal. It has occurred to me that there is the possibility of sampling at the peaks and valleys; but, there is also the possibility that the sampling could occur at the zero-crossings. In this latter case, every sample would be zero...


Real Input to Fixed Point Unscaled FFT

Started by kaly...@gmail.com in DSP & FPGA5 years ago

Hi all, I am working on FPGA Implementation of fixed-point FFT and trying to minimize resources. I have 4 parallel samples coming from ADC...

Hi all, I am working on FPGA Implementation of fixed-point FFT and trying to minimize resources. I have 4 parallel samples coming from ADC into FPGA. I want to calculate 1024-point FFT of the input stream. To do this, I have 4 FFT's of 256-point running in parallel. I am planning on multiplying the input stream with necessary twiddle factors before I send it to the 4 FFT's running in paralle...


Downconverting several band segments

Started by Justin Stocking in DSP & FPGA6 years ago

Hello. I am building an FPGA based software radio. It has a direct sampling ADC that then interfaces with the FPGA. My ADC has a 50 mhz...

Hello. I am building an FPGA based software radio. It has a direct sampling ADC that then interfaces with the FPGA. My ADC has a 50 mhz bandwidth, and I would like to selectively choose ~1 mhz to send to the computer for further processing. I would like to have 5 different "channels" (5 different segments) be able to be sent to the computer. I would like 200khz bandwidth at: 28mhz, 21mhz,...


Signal Processing In FPGA

Started by Filipe in DSP & FPGA7 years ago 1 reply

Hi guys, I am building a receiver and I will use FPGA to process the signal. My receiver has a front -end (antenna) a LNA, filter, and a A/D...

Hi guys, I am building a receiver and I will use FPGA to process the signal. My receiver has a front -end (antenna) a LNA, filter, and a A/D converter. After the A/D converter I need to process that signal in a FPGA and show the signal spectrum in a PC computer. I don't know what I can do after A/D converter. I am lost, because I don't know how the FPGA can process the signal. Does anybo...


Fixed Point Averaging

Started by kaly...@gmail.com in DSP & FPGA7 years ago

Hi all, I am working on an application which involves averaging of waveform records in FPGA. Averaging of waveforms can be done by 1)...

Hi all, I am working on an application which involves averaging of waveform records in FPGA. Averaging of waveforms can be done by 1) storing intermediate presum and then finally dividing it by N (total number of waveforms added) For example if we were to average 5 waveforms and 0.1, 0.3, 0.1, 0.4 are the values of the first point in each waveform set. The average of first point from...


Problem with Altera Video Input Daughtercard (DC-VIDEO-TVP5146N)

Started by gmdi...@gmail.com in DSP & FPGA7 years ago

Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to...

Hello, Does somebody work with DC-VIDEO-TVP5146N Altera kit (http://www.altera.com/products/devkits/altera/kit-daughtercard.html) ? I try to connect DC-VIDEO-TVP5146N to DK-NIOS-2S60N (http://www.altera.com/products/devkits/altera/kit-niosii-2S60.html) via SantaCruz interface. In fact I use NIOS with OpenCores i2c master to connect to TVP5146 video adc via i2c interface. The problem is tha...


Designing a filter with low cut off and very high sampling rate

Started by need...@yahoo.com in DSP & FPGA7 years ago

Hi All, I have to design a low pass bessel filter with bit rate of 100KHz. The cut off freq is .8* bit rate. The sampling frequensy is 100MHz....

Hi All, I have to design a low pass bessel filter with bit rate of 100KHz. The cut off freq is .8* bit rate. The sampling frequensy is 100MHz. The output of the filter should send data at the rate of 100MHz. I designed the filter using Matlab but the coeffient values are very small (10^-15). In the second order system, the coefficients are ok bu the gain is in the power of -14. I have to imp...


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