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I am looking at the design of a board using a ADSP-2191 connected to a host CPU via the host port. Reading the data sheet for the ADSP-2181 I see that there will be a 12~15 Thclk delay each time data is read from the host port. With a 40MHz hclk that would be a 375nS delay. What isn't clear from either the datasheet or hardware manual is whether this delay will still be present if I used the host port DMA to read a block of data. How I think things are supposed to work is that each time the host completes a read then the DMA will pre-fetch the next data. What I can't determine is if the host came to do the next transfer within the 12~15Thclk delay if it would have to wait for the transfer to complete, or is this delay only present in direct access mode. I have been unable to make any sense of the diagram 'Figure 8-16 Host Port DMA Read' in the hardware manual, there seems to be no relationship between HRDB and HACK, and no timing information is supplied. If anybody has any experience of the host port and can offer any help it would be much appreciated. Regards, Mark Darlington |
ADSP-2191 Host Port
Started by ●September 4, 2002
