i had posted a question regarding timing requirements (Sub:
Hardware : 21065L - Codec Interface(msg no. 1484)). i might reach a
conclusion, if the RFS assertion clock edge is known. i will explain
it as follows.
i wish to interface a codec with 21065L in multichannel mode. I could
able to sample the signal and playback the 48KHz. but i got confused
the synchronization issue. RFS is used as a frame sync for codec and
is generated by the processor. The CKRE bit of SRCTLx is setted
as '0' (samples at negative edge). whether at this same negative edge
of the BIT_CLK(external clk driven by the codec), the SPORT drives
(asserted) the RFS or the RFS is asserted at the +ve edge of the
BIT_CLK and the CKRE bit only says that the SPORT samples the
signals at negative edge( and not driving the RFS at -ve edges) .