|
Hello, I am working on a DSP project using ADSP 21065L Processor. I wish to configure extranal port DMA in Paced master mode for data accquision. Our application requires data to be accquired from slave device (ADC ) when ever device asserts DMARx signal. Iam assuming each time when device asserts DMARx pin, DMA controller performs only one transfer from extranal device to DSP internal memory and decrements the CEP0 register by one and waits for the next DMARx assertion even if CEP0 register is not equal to zero. Is my assumtion correct? In this way i need to accumalate set of data(say 256 samples from the same destination address) & to be stored in consecutive memory locations. I plan to intilize the DMA registers as follows. IIEP0 - Starting address of the sample set in the internal memory. IMEP0 -1 CEP0 - 256 (No. of samples) EIEP0 - Address of the extranal device. EMEP0- 0 ECEP0 - 1 With this configuration, i assume my core processor will be interrupted only after DMA controller accumalating 256 samples. Please clarify. Thank you very much kannan | |||||||
| |||||||
|
|
|||||||
Sharc DMA clarification
Started by ●May 4, 2000
Reply by ●May 4, 20002000-05-04
|
Kannan, All of your assumptions look correct to me. You will still have to figure out the DMAC register, but everything else looks right to me. Derek ----- Original Message ----- From: kannan <> To: <> Sent: Thursday, May 04, 2000 10:30 AM Subject: [adsp] Sharc DMA clarification > > Hello, > > I am working on a DSP project using ADSP 21065L Processor. I wish to > configure extranal > port DMA in Paced master mode for data accquision. > > Our application requires data to be accquired from slave device (ADC ) > when ever device > asserts DMARx signal. Iam assuming each time when device asserts DMARx > pin, DMA > controller performs only one transfer from extranal device to DSP > internal memory and > decrements the CEP0 register by one and waits for the next DMARx > assertion even if CEP0 > register is not equal to zero. Is my assumtion correct? > > In this way i need to accumalate set of data(say 256 samples from the > same destination > address) & to be stored in consecutive memory locations. I plan to > intilize the DMA registers > as follows. > > IIEP0 - Starting address of the sample set in the internal memory. > IMEP0 -1 > CEP0 - 256 (No. of samples) > EIEP0 - Address of the extranal device. > EMEP0- 0 > ECEP0 - 1 > > With this configuration, i assume my core processor will be interrupted > only after DMA > controller accumalating 256 samples. > Please clarify. > > Thank you very much > > kannan > You have a voice mail message waiting for you at iHello.com: > http://click.egroups.com/1/3555/4/_/8508/_/957453978/ > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.egroups.com/group/adsp > > Other Groups: http://www.dsprelated.com > |
