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Hi all, I have a custom board with 5 ADSP-21062 processors. 4 of the processors receive A/D data on their serial ports. The serial ports are configured for receiving two channels of 32-bit data. 2 of the processors (ID=2 and 4) work fine with no problems. The other two processors (ID=3 and 5) have a tendency to "slip" the data. What I mean by that is, the left channel will start out in the left channel and will slide from the left, through the frame sync, to the right channel and then back again. Almost like the frame sync is not there (which it is). And this process does not happen periodically, sometimes it takes a few seconds, sometimes 10-15 seconds in-between "jumps". All processors are running essentially the same code, all processors are getting the same clock signals, there are no reflections or noise in the clock signals. I am using DMA (with chaining enabled) to read in 512 words at a time. All the words in the block are skewed by the same amount (I know this because I have a test pattern going into each channel and can recognize the pattern). So, this says that the skew is happening whenever the DMA is being re-initialized. Does the serial port shut down while the DMA chaining is reloading? If so, why does this work on the other two processors and not these two? Anybody got any ideas? Jason Williams DAC Engineering Team Leader Digital Audio Corporation 5121 Holly Ridge Dr. Raleigh, NC 27612 http://www.dacaudio.com/ |
SPORT problems on 21062
Started by ●May 19, 2000
