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Hi, I must explain the setup of our custom board: we have two channels of two 65L each, connected in series within the channel. Each channel has access to a SDRAM bank which is shared for the two SHARCs. On the same bus is a host micro processor, which downloads the DSP code and other parameters via DMA to the SHARCs. Each time the SHARCs access the SDRAM, they lock the bus, so that the host does not interfere with the data transfer. I do this manually in the DSP (set and clear the bus lock bit in mode1 register) when there is an SDRAM access from the DSP. Sometimes this caused time-outs in the host, but I found a way in the host programming to work around it. I found that single SDRAM writes from the SHARC work fine, but block writes don't. This is probably due to this anomaly (from the Feb 17 2000 "ADSP-21065L Anomaly List for Revision 0.0, 0.1, 0.2, 0.3"): "BMAX-BTC failure in dual processor system with concurrent SDRAM accesses". What I do is interleave reads and writes (dummy read in my case) for block access. The IOCTL setting won't help in your case, since it is tailored to a different SDRAM type (the one I mentioned) - you will just have to consult the SDRAM data sheet an set the timing and access bits in the IOCTL accordingly. Regards, Andor > -----Ursprgliche Nachricht----- > Von: Jackie Chen [mailto:] > Gesendet am: Mittwoch, 7. Juni 2000 06:20 > An: > Betreff: about SDRAM interface > > Hello, > > I used NEC PD4564163G5-A10-9JF sdram for my > design , but it > can't work !! I tried many ways > but in vain .Could you offer me the information you mentioned > (IOCTL, bus > locking, etc.) ? I think it > could bring me some ideas to debug !! Thanks a lot!! > > Regards, > Jackie > - > Jackie Chen > Master of National Central University > Email : > Mobile: 0931536253 > Office : 886-3-4267387 > Fax : 886-3-4254501 |
AW: about SDRAM interface
Started by ●June 7, 2000
