Forums

Problems with the 21065L

Started by Ken Gracie August 18, 2000
Hi, everyone. I've posted this to comp.dsp as well. Ideas welcome...

I'm having some problems using/understanding the 21065L SHARC, and I
wonder if anyone has any insights:

1. Referencing External Memory

I'm developing an application that stores data in an external SDRAM.
As
I understand the manual, successive reads from consecutive external
addresses should be single-cycle, while reads from non-consecutive
addresses incur a penalty. I'm presently running the application in
the
VisualDSP simulator and seeing a penalty even for the former case,
and
a
larger than expected penalty in the latter. My register settings are
as
follows (the memory is attached to Bank 0 in the target hardware):

SYSCON=0x00000400
WAIT=0x21ad1b20
SDRDIV=0x000003a2
IOCTL=0xa8522000

These settings are consistent with my target hardware, which is a
Bittware Spinner board. I'm wondering if anyone has seen similar
behaviour, and whether I've set something incorrectly or just don't
have
an accurate understanding of the manual. 2. DMA

I want to send samples from the SHARC's internal memory through SPORT0
to a waiting DAC. I have successfully used DMA chaining to do this,
but
have had no luck with "one-shot" DMA where I set up a single DMA
transfer and then set up another in the SPORT0 Tx ISR. In fact, the
processor hangs and the interrupt never seems to be generated at all.
The data and non-DMA register settings are the same in both cases.
Again, this is intended to run on a Spinner board. Any thoughts, insights or ideas would be most welcome.

Thanks,
Ken.



Problems installing Visual DSP.

IT sounds weird, bnut visual DSP doesn't want to recognize my board.

I've the old EZ-KIT for 21060 and it works fine. Bt I really can't use the
debugger , I don't have the COM setings in the Seting menu.

Anyone had the same problem?

DSPDEV.com
DSP developement for Audio applications.
Nicolas Choukroun
tel : 33(1) 56 32 32 22
Fax : 33(1) 56 32 32 23
----- Original Message -----
From: "Ken Gracie" <>
To: <>
Sent: Friday, August 18, 2000 4:39 PM
Subject: [adsp] Problems with the 21065L > Hi, everyone. I've posted this to comp.dsp as well. Ideas welcome...
>
> I'm having some problems using/understanding the 21065L SHARC, and I
> wonder if anyone has any insights:
>
> 1. Referencing External Memory
>
> I'm developing an application that stores data in an external SDRAM.
> As
> I understand the manual, successive reads from consecutive external
> addresses should be single-cycle, while reads from non-consecutive
> addresses incur a penalty. I'm presently running the application in
> the
> VisualDSP simulator and seeing a penalty even for the former case,
> and
> a
> larger than expected penalty in the latter. My register settings are
> as
> follows (the memory is attached to Bank 0 in the target hardware):
>
> SYSCON=0x00000400
> WAIT=0x21ad1b20
> SDRDIV=0x000003a2
> IOCTL=0xa8522000
>
> These settings are consistent with my target hardware, which is a
> Bittware Spinner board. I'm wondering if anyone has seen similar
> behaviour, and whether I've set something incorrectly or just don't
> have
> an accurate understanding of the manual. > 2. DMA
>
> I want to send samples from the SHARC's internal memory through SPORT0
> to a waiting DAC. I have successfully used DMA chaining to do this,
> but
> have had no luck with "one-shot" DMA where I set up a single DMA
> transfer and then set up another in the SPORT0 Tx ISR. In fact, the
> processor hangs and the interrupt never seems to be generated at all.
> The data and non-DMA register settings are the same in both cases.
> Again, this is intended to run on a Spinner board. > Any thoughts, insights or ideas would be most welcome.
>
> Thanks,
> Ken. >
>
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