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Dear list, I'm working on a project with the ADSP-2181, where I have 8-bit RAM and ROM chips, and an LCD panel, on the bus. The memory chips and LCD are pretty slow, so I'm using 5 to 7 waitstates with them all. Meanwhile I have a time-critical ISR that is called 625 times per second. My question is, what does the DSP actually _do_ during all those waitstates? If I am doing a BDMA transfer with 5 waitstates, does the BDMA steal one cycle per word transferred, or six? I believe that an instruction accessing the external memory with 5 waitstates will take 6 cycles to complete, and the processor can't execute any more instructions in those 5 extra cycles. But I don't understand how it works with BDMA. Thanks for your input Steve Conner Electronic Engineer Optosci Ltd. |
ADSP-21xx waitstate question
Started by ●January 28, 2004
