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Hi all I am testing SPORT multch channel mode DMA Transfer with chainnig on 21161. DMA GP registor is not 0 I wrote program it while (!Data_Ready) { asm("idle;"); Data_Ready = *(int *)GP0A; { Data_Ready = 0; DMA transfer Isr out,program run out while loop. This time, Isr out seems to be late. What does the factor kept waiting consider? I want your suggestion. Thank you . JVC DSP Engineer |
SPORT DMA transfer Isr out late?
Started by ●March 23, 2004
