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FW: Boot form Flash to SDRAM with VDK

Started by Hemant Sadhwani ●February 22, 2005


-----Original Message-----
From: Hemant Sadhwani
Sent: Tuesday, February 22, 2005 8:49 PM
To: 'Mike Rosing'
Subject: RE: [adsp] Boot form Flash to SDRAM with VDK

Hello Mike,

Yes you were right in your assumption as it was Blackfin. At present I'm
working with this "VDK_blink_with_two_threads_messages" and only tiring to
execute from the .dxe. I've made it very simple that I want cache enabled and
place all program code into SDRAM and execute it from there.

Please find one loader file attached. At least have a look on loader file and
if possible let me know where I'm utterly wrong.

As far as my understanding says it should work coz I've made mem_EVT sections
placed in SDRAM memory then place sec_VDK_strt and then program but I don't
know why control is not passed to 0x00000000 after RUN.

If possible please let me know what is sec_VDK_strt in loader file.

Regards,
Hemant Sadhwani -----Original Message-----
From: Mike Rosing [mailto:]
Sent: Tuesday, February 22, 2005 8:17 PM
To: Hemant Sadhwani
Cc:
Subject: Re: [adsp] Boot form Flash to SDRAM with VDK

On Tue, 22 Feb 2005, Hemant Sadhwani wrote:

> I'm struggling to boot from FLASH and load the program code into SDRAM and
> data code into L1 data RAM and configure L1 instruction memory as a cache.
I
> do have an example which is go it from the Analog Devices site i.e.
> "application Code with Application Init" But the example only mentions of
> assembly and without VDK. But I'm working on example provided by Analog
> Device i.e." VDK_blink_with_two_threads_messages" which is executing from
the
> L1 Instruction memory and I'm trying to boot it into SDRAM and execute it
> from there only. But I'm unable to do so, can anybody help me get out of
> situation or please give me link or some reference .LDF file so that I
could
> get out of dead lock.

I assume this is with the Blackfin? You need to read up on the linker
file and look for the keyword "overlay". What you want to do is have the
linker put in all the addresses for the run space, and have the loader
burn everything into flash space. You also need a boot loader that will
copy from flash to the correct ram address, then jump to it. ADI supplies
those, but it is easy enough to write your own.

Patience, persistence, truth,
Dr. mike


/*
** Default LDF for a VDK project on the ADSP-BF533.
**
** There are configuration options that can be specified either by compiler
** flags, or by linker flags directly. These options are:
**
** __WORKAROUNDS_ENABLED
** Defined by compiler when -workaround is used to direct LDF to
** link with libraries that have been built with work-arounds enabled.
** USE_CACHE
** Makes use of some L1 memory as cache. Implies the presence of at
** least some external memory.
*/

// Setup the architecture
ARCHITECTURE(ADSP-BF533)

// Setup the search directories
SEARCH_DIR( $ADI_DSP/BLACKFIN/lib )

// Include the VDK preprocessor macros
#define VDK_LDF_
#include "VDK.h"

// Setup the VDK library preprocessor macros
#define USE_CACHE 1

#if VDK_INSTRUMENTATION_LEVEL_==2
#define VDK_IFLAG_ i
#elif VDK_INSTRUMENTATION_LEVEL_==1
#define VDK_IFLAG_ e
#else
#define VDK_IFLAG_ n
#endif

#ifdef __WORKAROUNDS_ENABLED
#define RT_LIB_NAME(x) lib ## x ## y.dlb
#define RT_OBJ_NAME(x) x ## y.doj
#else
#define RT_LIB_NAME(x) lib ## x ## .dlb
#define RT_OBJ_NAME(x) x ## .doj
#endif

#define OMEGA RT_OBJ_NAME(idle532mt)

#define MEMINIT __initsbsz532.doj

#ifdef IEEEFP
#define FPLIBS RT_LIB_NAME(sftflt532), RT_LIB_NAME(dsp532)
#else
#define FPLIBS RT_LIB_NAME(dsp532), RT_LIB_NAME(sftflt532)
#endif

$LIBRARIES = RT_LIB_NAME(small532mt), MEMINIT, RT_LIB_NAME(c532mt), RT_LIB_NAME(event532mt), RT_LIB_NAME(io532_mt), RT_LIB_NAME(cpp532mt), RT_LIB_NAME(cpprt532mt), FPLIBS, RT_LIB_NAME(rt_fileio532mt), RT_LIB_NAME(m3free532), libetsi532.dlb, OMEGA;

$BASE_LIBRARIES = $LIBRARIES;

#ifdef __WORKAROUNDS_ENABLED
#define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -BF532_Y.dlb
#define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
$LIBS = VDK-CORE-BF532.dlb, VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;
#else // __WORKAROUNDS_ENABLED
#define VDK_LIB_NAME_MACRO_(x) vdk- ## x ## -BF532.dlb
#define VDK_LIB_NAME_(x) VDK_LIB_NAME_MACRO_(x)
$LIBS = VDK-CORE-BF532.dlb, VDK_LIB_NAME_(VDK_IFLAG_), $BASE_LIBRARIES;
#endif // __WORKAROUNDS_ENABLED

$OBJS = $COMMAND_LINE_OBJECTS, cplbtab533.doj, RT_OBJ_NAME(crtn532);

//
// Memory map.
//
// The known memory spaces are as follows:
//
// 0xFFE00000 - 0xFFFFFFFF Core MMR registers (2MB)
// 0xFFC00000 - 0xFFDFFFFF System MMR registers (2MB)
// 0xFFB01000 - 0xFFBFFFFF Reserved
// 0xFFB00000 - 0xFFB00FFF Scratch SRAM (4K)
// 0xFFA14000 - 0xFFAFFFFF Reserved
// 0xFFA10000 - 0xFFA13FFF Code SRAM / cache (16K)
// 0xFFA00000 - 0xFFA0FFFF Code SRAM (64K)
// 0xFF908000 - 0xFF9FFFFF Reserved
// 0xFF904000 - 0xFF907FFF Data Bank B SRAM / cache (16K)
// 0xFF900000 - 0xFF903FFF Data Bank B SRAM (16K)
// 0xFF808000 - 0xFF8FFFFF Reserved
// 0xFF804000 - 0xFF807FFF Data Bank A SRAM / cache (16K)
// 0xFF800000 - 0xFF803FFF Data Bank A SRAM (16K)
// 0xEF000000 - 0xFF7FFFFF Reserved
// 0x00000000 - 0xEEFFFFFF unpopulated
// MEMORY
{
// mem_VDK_strt { TYPE(RAM) START(0xFFA00000) END(0xFFA00003) WIDTH(8) }
// mem_l1_code { TYPE(RAM) START(0xFFA00004) END(0xFFA0FFFF) WIDTH(8) }
mem_l1_code_cache { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }

// The mem_EVT sections should be placed in data memory

#ifdef USE_CACHE
//mem_l1_data_a_cache { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }
mem_EVT_all { TYPE(RAM) START(0x00000000) END(0x00000003) WIDTH(8) }
mem_EVT_NMI { TYPE(RAM) START(0x00000004) END(0x00000007) WIDTH(8) }
mem_EVT_EVX { TYPE(RAM) START(0x00000008) END(0x0000000B) WIDTH(8) }
mem_EVT_IRPTEN { TYPE(RAM) START(0x0000000C) END(0x0000000F) WIDTH(8) }
mem_EVT_IVHW { TYPE(RAM) START(0x00000010) END(0x00000013) WIDTH(8) }
mem_EVT_IVTMR { TYPE(RAM) START(0x00000014) END(0x00000017) WIDTH(8) }
mem_EVT_IVG7 { TYPE(RAM) START(0x00000018) END(0x0000001B) WIDTH(8) }
mem_EVT_IVG8 { TYPE(RAM) START(0x0000001C) END(0x0000001F) WIDTH(8) }
mem_EVT_IVG9 { TYPE(RAM) START(0x00000020) END(0x00000023) WIDTH(8) }
mem_EVT_IVG10 { TYPE(RAM) START(0x00000024) END(0x00000027) WIDTH(8) }
mem_EVT_IVG11 { TYPE(RAM) START(0x00000028) END(0x0000002B) WIDTH(8) }
mem_EVT_IVG12 { TYPE(RAM) START(0x0000002C) END(0x0000002F) WIDTH(8) }
mem_EVT_IVG13 { TYPE(RAM) START(0x00000030) END(0x00000033) WIDTH(8) }
mem_EVT_IVG14 { TYPE(RAM) START(0x00000034) END(0x00000037) WIDTH(8) }
mem_EVT_IVG15 { TYPE(RAM) START(0x00000038) END(0x0000003B) WIDTH(8) }

mem_data { TYPE(RAM) START(0x0000003C) END(0x000037FF) WIDTH(8) }
mem_sysstack { TYPE(RAM) START(0x00003800) END(0x00003FFF) WIDTH(8) }
mem_heap { TYPE(RAM) START(0x00004000) END(0x00007FFF) WIDTH(8) }
mem_l1_scratch { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }
mem_sdram0 { TYPE(RAM) START(0x00008000) END(0x07FFFFFF) WIDTH(8) }
#endif
} PROCESSOR p0
{
OUTPUT( $COMMAND_LINE_OUTPUT_FILE )
KEEP(VDK_strt,_main)

SECTIONS
{
sec_EVT_all { INPUT_SECTIONS( $OBJS( seg_EVT_all ) $LIBS( seg_EVT_all ) ) } > mem_EVT_all
sec_EVT_NMI { INPUT_SECTIONS( $OBJS( seg_EVT_NMI ) $LIBS( seg_EVT_NMI ) ) } > mem_EVT_NMI
sec_EVT_EVX { INPUT_SECTIONS( $OBJS( seg_EVT_EVX ) $LIBS( seg_EVT_EVX ) ) } > mem_EVT_EVX
sec_EVT_IRPTEN { INPUT_SECTIONS( $OBJS( seg_EVT_IRPTEN ) $LIBS( seg_EVT_IRPTEN ) ) } > mem_EVT_IRPTEN
sec_EVT_IVHW { INPUT_SECTIONS( $OBJS( seg_EVT_IVHW ) $LIBS( seg_EVT_IVHW ) ) } > mem_EVT_IVHW
sec_EVT_IVTMR { INPUT_SECTIONS( $OBJS( seg_EVT_IVTMR ) $LIBS( seg_EVT_IVTMR ) ) } > mem_EVT_IVTMR
sec_EVT_IVG7 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG7 ) $LIBS( seg_EVT_IVG7 ) ) } > mem_EVT_IVG7
sec_EVT_IVG8 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG8 ) $LIBS( seg_EVT_IVG8 ) ) } > mem_EVT_IVG8
sec_EVT_IVG9 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG9 ) $LIBS( seg_EVT_IVG9 ) ) } > mem_EVT_IVG9
sec_EVT_IVG10 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG10 ) $LIBS( seg_EVT_IVG10 ) ) } > mem_EVT_IVG10
sec_EVT_IVG11 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG11 ) $LIBS( seg_EVT_IVG11 ) ) } > mem_EVT_IVG11
sec_EVT_IVG12 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG12 ) $LIBS( seg_EVT_IVG12 ) ) } > mem_EVT_IVG12
sec_EVT_IVG13 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG13 ) $LIBS( seg_EVT_IVG13 ) ) } > mem_EVT_IVG13
sec_EVT_IVG14 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG14 ) $LIBS( seg_EVT_IVG14 ) ) } > mem_EVT_IVG14
sec_EVT_IVG15 { INPUT_SECTIONS( $OBJS( seg_EVT_IVG15 ) $LIBS( seg_EVT_IVG15 ) ) } > mem_EVT_IVG15 /* sec_VDK_strt
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $LIBS(sec_VDK_strt) )
} >mem_sdram0
*/
sec_program
{
INPUT_SECTION_ALIGN(2)
INPUT_SECTIONS( $LIBS(sec_VDK_strt) )
INPUT_SECTIONS( $OBJS(program) $LIBS(program) )
INPUT_SECTIONS( $OBJS(noncache_code) $LIBS(noncache_code))
INPUT_SECTIONS( $LIBS(VDK_ISR_code) )
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS( $OBJS(L1_code) $LIBS(L1_code))
} >mem_sdram0

l1_code
{
#ifdef USE_CACHE /* { */
___l1_code_cache = 1;
___l1_data_cache_a = 1;
___l1_data_cache_b = 1;
#else
___l1_code_cache = 0;
___l1_data_cache_a = 0;
___l1_data_cache_b = 0;
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(program) $LIBS(program))
INPUT_SECTIONS( $LIBS(VDK_ISR_code) )
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS( $OBJS(L1_code) $LIBS(L1_code))
#endif /* USE_CACHE } */
} >mem_l1_code_cache

data
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS($OBJS(data1) $LIBS(data1))
INPUT_SECTIONS($OBJS(voldata) $LIBS(voldata))
INPUT_SECTIONS($OBJS(constdata) $LIBS(constdata))
INPUT_SECTIONS( $OBJS(L1_data_b) $LIBS(L1_data_b))
INPUT_SECTIONS( $OBJS(cplb_data) $LIBS(cplb_data))
INPUT_SECTIONS( $LIBS(ctor) $OBJS(ctor) )
INPUT_SECTIONS( $LIBS(ctorl) $OBJS(ctorl) )
INPUT_SECTIONS( $OBJS(.gdt) $LIBS(.gdt) )
INPUT_SECTIONS( $OBJS(.gdtl) $LIBS(.gdtl) )
INPUT_SECTIONS( $OBJS(.edt) $LIBS(.edt) )
INPUT_SECTIONS( $OBJS(.cht) $LIBS(.cht) )
INPUT_SECTIONS( $OBJS(.frt) $LIBS(.frt) )
INPUT_SECTIONS( $OBJS(.frtl) $LIBS(.frtl) )
} >mem_data //mem_l1_data_b

#ifdef USE_CACHE
bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz) $LIBS(bsz))
} >mem_sdram0

bsz_init
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz_init) $LIBS(bsz_init))
} >mem_sdram0

.meminit {} >mem_sdram0
#else
bsz ZERO_INIT
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz) $LIBS(bsz))
} >mem_data //mem_l1_data_b

bsz_init
{
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(bsz_init) $LIBS(bsz_init))
} >mem_data //mem_l1_data_b

.meminit {} >mem_data //mem_l1_data_b
#endif

sysstack
{
ldf_sysstack_space = .;
ldf_sysstack_end = ldf_sysstack_space + MEMORY_SIZEOF(mem_sysstack);
ldf_sysstack_length = ldf_sysstack_end - ldf_sysstack_space;
} >mem_sysstack

sec_heap
{
// Allocate a heap for the application
ldf_heap_space = .;
ldf_heap_end = ldf_heap_space + MEMORY_SIZEOF(mem_heap) - 1;
ldf_heap_length = ldf_heap_end - ldf_heap_space;
} >mem_heap
/*
sdram
{
#ifdef USE_CACHE
INPUT_SECTION_ALIGN(4)
INPUT_SECTIONS( $OBJS(sdram0) $LIBS(sdram0))
INPUT_SECTIONS( $OBJS(noncache_code) $LIBS(noncache_code))
INPUT_SECTIONS( $OBJS(program) $LIBS(program) )
INPUT_SECTIONS( $OBJS(cplb) $LIBS(cplb))
INPUT_SECTIONS( $OBJS(cplb_code) $LIBS(cplb_code))
INPUT_SECTIONS( $OBJS(data1) $LIBS(data1))
INPUT_SECTIONS( $OBJS(voldata) $LIBS(voldata))
INPUT_SECTIONS($OBJS(constdata) $LIBS(constdata))
INPUT_SECTIONS( $OBJS(cplb_data) $LIBS(cplb_data))
#endif
} >mem_sdram0
*/
}

}

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Reply by Mike Rosing ●February 22, 20052005-02-22
On Tue, 22 Feb 2005, Hemant Sadhwani wrote:

> Yes you were right in your assumption as it was Blackfin. At present I'm
> working with this "VDK_blink_with_two_threads_messages" and only tiring to
> execute from the .dxe. I've made it very simple that I want cache enabled and
> place all program code into SDRAM and execute it from there.
>
> Please find one loader file attached. At least have a look on loader file and
> if possible let me know where I'm utterly wrong.
>
> As far as my understanding says it should work coz I've made mem_EVT sections
> placed in SDRAM memory then place sec_VDK_strt and then program but I don't
> know why control is not passed to 0x00000000 after RUN.
>
> If possible please let me know what is sec_VDK_strt in loader file.

A zeroth order looks says sec_VDK_strt is at location 0x8000. sec_EVT_all
is at location 0. Maybe that's a reset vector, and you need to setup the
vectors to point to your starting address.

I can't say I understand any of it though, so good luck!

Patience, persistence, truth,
Dr. mike