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BF531 : PLL Settings

Started by Chinmoy Raj H March 22, 2005

Hi,

I wish to configure my BF531 to work at max CCLK of 400MHz and max SCLK of 133MHz.

Two options :-

1. I can use a 8MHz crystal.
Set DF bit to 1.
Set the multiplier (MSEL[5:0]) to 50 to get VCO = 400MHz.
Set Core Clock Divider to 1 (CSEL[1:0] = 00) to get CCLK = 400MHz.
Set System Clock Divider to 3 (SSEL[3:0] = 0011) to get SCLK = 133.33MHz.
I think SCLK will be by itself rounded off to 133MHz right ?

or

2. Use a clock generator to generate a Clock = 27MHz (as has been done in the EZ-Lite, refer to DSP_CLK signal).
Set DF bit to 1.
Set the multiplier (MSEL[5:0]) to 14 to get VCO = 378MHz.
Set Core Clock Divider to 1 (CSEL[1:0] = 00) to get CCLK = 378MHz.
Set System Clock Divider to 3 (SSEL[3:0] = 0011) to get SCLK = 126MHz.
Setting the multiplier to 15 will make VCO = 405MHz (which will exceed 400MHz). Hence cant do that right ?
Having SCLK = 126MHz will disable me from using the SDRAM at the max ferq of 133MHz. If the DSP_CLK of the EZ-Lite is 26.67MHz, using a multiplier of 15 will give me CCLK=VCO@0MHz and
than SCLK= 133MHz.
What is the DSP_CLK set to on the EZ-LITE (BF533) any idea ? As per the gut feeling goes, Clock Generator output will be better than that from the Crystal output.

What do you suggest out of the two options ?

Any other alternatives of configuration, pls suggest.

Waiting eagerly for your reply,

Regards,
Chinmoy.