Forums

Re: BF531 : PLL Settings

Started by sink...@gmail.com February 20, 2006
	Hi,

I wish to configure my BF531 to work at max CCLK of 400MHz and max SCLK of
133MHz.
Two options :-
1. I can use a 8MHz crystal.
Set DF bit to 1.
Set the multiplier (MSEL[5:0]) to 50 to get VCO = 400MHz.
Set Core Clock Divider to 1 (CSEL[1:0] = 00) to get CCLK = 400MHz.
Set System Clock Divider to 3 (SSEL[3:0] = 0011) to get SCLK = 133.33MHz. 
I think SCLK will be by itself rounded off to 133MHz right ?
or 
2. Use a clock generator to generate a Clock = 27MHz (as has been done in the
EZ-Lite, refer to DSP_CLK signal).
Regards,
Chinmoy.

>> Just cross check.. Can the BF take a clock i/p
at 8MHZ.. I worked with BF-533 before and valid CLK_IN range was 10MHz to 40
MHz.. Just make sure that you dont mess up the design by going out of spec
... kafka