Hello! We're using SPORT in multichannel autobuffer mode, SCLK and
TFS/RFS are generated externally.
After some special signal becomes high (let's call it RESET)
SCLK/TFS/RFS are masked and SPORT should be disabled by DSP.
When RESET becomes low SPORT needs to be reenabled.
But after reenabling SPORT we have some corrupted data at DT. And (as
we suppose) because RESET is async with DSP some internal
counters/buffers e.t.s of SPORT remains at their last state.
How to reset SPORT by DSP to state that it was just after hardware
reset?
ADSP 219x SPORT disable/enable
Started by ●February 1, 2009
Reply by ●February 1, 20092009-02-01
Hello,
I've never used 219x, but had similar problems with 218x SPORTS. The ADI
documentation on how these work (for 218x) is a little vague and it's
not clear that there's any reliable way resetting them. An ADI tech
support guy told me that just disabling them, re-initialising them,
waiting for a frame or so and then re-enabling them should be equivalent
to a hardware reset, but I never got this to work.
It seems to me that once they've gone wrong they tend to stay wrong and
the only reliable way to get them right again is full hardware reset and
processor re-boot. At least that's what I ended up doing in the end.
If you're lucky enough to get to speak to someone at ADI who really
knows what they're talking about re. this stuff you might get better
advice, but this is not so easy these days :-(
Regards
--
Adrian Hey
nickolayorekhov wrote:
> Hello! We're using SPORT in multichannel autobuffer mode, SCLK and
> TFS/RFS are generated externally.
> After some special signal becomes high (let's call it RESET)
> SCLK/TFS/RFS are masked and SPORT should be disabled by DSP.
>
> When RESET becomes low SPORT needs to be reenabled.
> But after reenabling SPORT we have some corrupted data at DT. And (as
> we suppose) because RESET is async with DSP some internal
> counters/buffers e.t.s of SPORT remains at their last state.
>
> How to reset SPORT by DSP to state that it was just after hardware
> reset?
>
> ______________________________________________________________________
> This email has been scanned by the MessageLabs Email Security System.
> For more information please visit http://www.messagelabs.com/email
> ______________________________________________________________________
I've never used 219x, but had similar problems with 218x SPORTS. The ADI
documentation on how these work (for 218x) is a little vague and it's
not clear that there's any reliable way resetting them. An ADI tech
support guy told me that just disabling them, re-initialising them,
waiting for a frame or so and then re-enabling them should be equivalent
to a hardware reset, but I never got this to work.
It seems to me that once they've gone wrong they tend to stay wrong and
the only reliable way to get them right again is full hardware reset and
processor re-boot. At least that's what I ended up doing in the end.
If you're lucky enough to get to speak to someone at ADI who really
knows what they're talking about re. this stuff you might get better
advice, but this is not so easy these days :-(
Regards
--
Adrian Hey
nickolayorekhov wrote:
> Hello! We're using SPORT in multichannel autobuffer mode, SCLK and
> TFS/RFS are generated externally.
> After some special signal becomes high (let's call it RESET)
> SCLK/TFS/RFS are masked and SPORT should be disabled by DSP.
>
> When RESET becomes low SPORT needs to be reenabled.
> But after reenabling SPORT we have some corrupted data at DT. And (as
> we suppose) because RESET is async with DSP some internal
> counters/buffers e.t.s of SPORT remains at their last state.
>
> How to reset SPORT by DSP to state that it was just after hardware
> reset?
>
> ______________________________________________________________________
> This email has been scanned by the MessageLabs Email Security System.
> For more information please visit http://www.messagelabs.com/email
> ______________________________________________________________________
Reply by ●February 2, 20092009-02-02
Hi,
I would like to know if it is possible to use DDR SDRAM instead SDR SDRAM with the 2137x ?
The reason for this is that DDR seems to be less expensive.
Something like
http://www.samsung.com/global/system/business/semiconductor/product/2008/11/26/851438ds_k4h51xx38f_tsop2_rev11.pdf
I understand that DDR operates on both rising and falling edges of the clocks, but after all, why would it be a problem when it is controlled by a SDR SDRAM controller ?
I see that the command set is exactly the same except that the DDR has an added "Extended Mode Register Set" command which our SDRAM controller would not use anyway.
If it is possible, how should that be connected ? is CK connected to clock like for SDRAM but \CK is tighed to ground ?
The same question could apply for DDR2 and DDR3, i haven't looked at those really...
Thanks,
Laurent
_________________________________________________________________
Windows Live Hotmailmore than just e-mail.
http://windowslive.com/howitworks?ocid=TXT_TAGLM_WL_t2_hm_justgotbetter_howitworks_012009
I would like to know if it is possible to use DDR SDRAM instead SDR SDRAM with the 2137x ?
The reason for this is that DDR seems to be less expensive.
Something like
http://www.samsung.com/global/system/business/semiconductor/product/2008/11/26/851438ds_k4h51xx38f_tsop2_rev11.pdf
I understand that DDR operates on both rising and falling edges of the clocks, but after all, why would it be a problem when it is controlled by a SDR SDRAM controller ?
I see that the command set is exactly the same except that the DDR has an added "Extended Mode Register Set" command which our SDRAM controller would not use anyway.
If it is possible, how should that be connected ? is CK connected to clock like for SDRAM but \CK is tighed to ground ?
The same question could apply for DDR2 and DDR3, i haven't looked at those really...
Thanks,
Laurent
_________________________________________________________________
Windows Live Hotmailmore than just e-mail.
http://windowslive.com/howitworks?ocid=TXT_TAGLM_WL_t2_hm_justgotbetter_howitworks_012009
Reply by ●February 3, 20092009-02-03
Ooops, i realized that DDR does not come up in 3.3v ...
Laurent
To: a...From: s...@msn.comDate: Mon, 2 Feb 2009 09:58:19 -0800Subject: [adsp] Using DDR SDRAM on SHARC 2137x
Hi, I would like to know if it is possible to use DDR SDRAM instead SDR SDRAM with the 2137x ?The reason for this is that DDR seems to be less expensive. Something likehttp://www.samsung.com/global/system/business/semiconductor/product/2008/11/26/851438ds_k4h51xx38f_tsop2_rev11.pdf I understand that DDR operates on both rising and falling edges of the clocks, but after all, why would it be a problem when it is controlled by a SDR SDRAM controller ?I see that the command set is exactly the same except that the DDR has an added "Extended Mode Register Set" command which our SDRAM controller would not use anyway.If it is possible, how should that be connected ? is CK connected to clock like for SDRAM but \CK is tighed to ground ? The same question could apply for DDR2 and DDR3, i haven't looked at those really... Thanks,Laurent
Windows Live Hotmailmore than just e-mail. See how it works.
_________________________________________________________________
Windows Live Hotmailmore than just e-mail.
http://windowslive.com/howitworks?ocid=TXT_TAGLM_WL_t2_hm_justgotbetter_howitworks_012009
Laurent
To: a...From: s...@msn.comDate: Mon, 2 Feb 2009 09:58:19 -0800Subject: [adsp] Using DDR SDRAM on SHARC 2137x
Hi, I would like to know if it is possible to use DDR SDRAM instead SDR SDRAM with the 2137x ?The reason for this is that DDR seems to be less expensive. Something likehttp://www.samsung.com/global/system/business/semiconductor/product/2008/11/26/851438ds_k4h51xx38f_tsop2_rev11.pdf I understand that DDR operates on both rising and falling edges of the clocks, but after all, why would it be a problem when it is controlled by a SDR SDRAM controller ?I see that the command set is exactly the same except that the DDR has an added "Extended Mode Register Set" command which our SDRAM controller would not use anyway.If it is possible, how should that be connected ? is CK connected to clock like for SDRAM but \CK is tighed to ground ? The same question could apply for DDR2 and DDR3, i haven't looked at those really... Thanks,Laurent
Windows Live Hotmailmore than just e-mail. See how it works.
_________________________________________________________________
Windows Live Hotmailmore than just e-mail.
http://windowslive.com/howitworks?ocid=TXT_TAGLM_WL_t2_hm_justgotbetter_howitworks_012009
