Hello,
I have measured a very high latency when trying to transmit a single quad word
from the DSP to a Virtex5 FPGA on the other side.
I am using the flag outputs as my indicators. I am raising one flag just before
I write the quad word to the transmitter buffer (1):
tempreg = __builtin_sysreg_read(__FLAGREG);
tempreg |= FLAGREG_FLAG0_OUT;
__builtin_sysreg_write(__FLAGREG, tempreg);
__builtin_sysreg_write4(__LBUFTX1, *sendquad);
Another flag is raised inside the RX interrupt handler just after reading the RX
buffer (2).
There is two more flags raised by the FPGA. One is set when the first rising
edge of the DSP TX clock signal is detected (3). Another one is set when the
whole quad word is written to the receiver FIFO in the FPGA (4).
Taking the first flag (1 )as the reference point the latency measured with
respect to all other flags is around 100 ms, which seems to be way to much.
The time difference between the first rising edge of the DSP RX (2), the
reception of the whole quad word by the FPGA (3) and also echoing the data back
to the DSP is very small (4). This means that the DSP seems to be waiting before
it starts transmitting what I wrote to the TX buffer for around 100 ms.
Has anyone encountered this behavior and has any comments or hints?
I am not using DMA.
