Hi,
I am using TMS320F2812's McBSP in ClockStop Mode (SPI mode). I
have the settings as mentioned in the Chapter 2.3 (SPI Protocol) in
the SPRU061B. I am able to see the data transmitted on the DX pin and
the FSX signal (Chip Enable signal) on the FSX pin of the board.
My issue is that, I am not able to see the clock signal on CLKX pin,
when the data is being transmitted on my oscilloscope. I am herewith
sending my code. Kindly tell me whether I am wrong somewhere. I need
this because, I have to do an interprocessor communication.
/******************************************************************************************/
#include "DSP281x_Device.h" // DSP281x Headerfile Include File
#include "DSP281x_Examples.h" // DSP281x Examples Include File
//#include"lcd_cmd.h"
// Define the level of the FIFO 1-16
#define FIFO_LEVEL 16
// Choose a word size. Uncomment one of the following lines
// #define WORD_SIZE 8 // Run a loopback test in 8-bit mode
#define WORD_SIZE 16 // Run a loopback test in 16-bit mode
//#define WORD_SIZE 32 // Run a loopback test in 32-bit mode
// Prototype statements for functions found within this file.
void delay_loop(void);
void init_mcbsp(void);
void mcbsp_xmit(int a, int b);
void mcbsp_fifo_init(void);
void error(void);
void init_mcbsp_16bitspi(void);
// Global data for this example
Uint16 sdata1 = 0x000; // Sent Data
Uint16 rdata1 = 0x000; // Recieved Data
Uint16 sdata2 = 0x000; // Sent Data
Uint16 rdata2 = 0x000; // Recieved Data
Uint16 rdata1_point;
Uint16 rdata2_point;
void main(void)
{
Uint16 i,j,k;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP281x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP281x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this example, only enable the GPIO for McBSP
EALLOW;
GpioMuxRegs.GPFMUX.all=0x7E00; // Select GPIOs to be McBSP pins
// Port F MUX - x111 1110 0000 0000
EDIS;
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP281x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP281x_DefaultIsr.c.
// This function is found in DSP281x_PieVect.c.
InitPieVectTable();
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP281x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// mcbsp_fifo_init(); // Initialize the Mcbsp FIFO
init_mcbsp(); // Initalize the Mcbsp in loopback test mode
// Step 5. User specific code, enable interrupts:
init_mcbsp_16bitspi();
sdata2 = 0x0000; // value is a don't care for 16-bit
mode
sdata1 = 0x0001; // 16-bit value to send
rdata1_point = sdata1;
while(1)
{
for(j=0;j<20;j++)
{
while(!McbspaRegs.SPCR2.bit.XRDY){}
for(i = 1; i <= FIFO_LEVEL; i++)
{
mcbsp_xmit(sdata1,sdata2);
sdata1++;
}
// while(McbspaRegs.MFFRX.bit.RXFFST != FIFO_LEVEL ) { }
// Check for receive
/* for(i = 1; i <= FIFO_LEVEL; i++)
{
rdata1 = McbspaRegs.DRR1.all;
asm(" nop"); // read DRR1
//if(rdata1 != rdata1_point) error();
// rdata1_point++;
}*/
asm(" nop");
}
k=0;
}
}
/*void mcbsp_fifo_init()
{
McbspaRegs.MFFTX.all=0x0000 ;
McbspaRegs.MFFRX.all=0x001F;
McbspaRegs.MFFCT.all=0x0;
McbspaRegs.MFFINT.all=0x0;
McbspaRegs.MFFST.all=0x0;
McbspaRegs.MFFTX.bit.MFFENA=1; // Enable FIFO Enhancements
McbspaRegs.MFFTX.bit.TXFIFO_RESET=1; // Re-Enable Transmit channel
McbspaRegs.MFFRX.bit.RXFIFO_RESET=1; // Enable Receive channel
}
*/
void init_mcbsp()
{
//SPCR2 Register = 0x00
McbspaRegs.SPCR2.bit.rsvd = 0x0;//15,14,13,12,11,10
McbspaRegs.SPCR2.bit.FREE = 0x0;//9
McbspaRegs.SPCR2.bit.SOFT = 0x0;//8
McbspaRegs.SPCR2.bit.FRST = 0x0;//7
McbspaRegs.SPCR2.bit.GRST = 0x0;//6
McbspaRegs.SPCR2.bit.XINTM = 0x0;//5,4
McbspaRegs.SPCR2.bit.XSYNCERR = 0x0;//3
McbspaRegs.SPCR2.bit.XEMPTY = 0x0;//2
McbspaRegs.SPCR2.bit.XRDY = 0x0;//1
McbspaRegs.SPCR2.bit.XRST = 0x0;//0
// McbspaRegs.SPCR1.all=0x0000;
McbspaRegs.SPCR1.bit.DLB = 0x0;//15
McbspaRegs.SPCR1.bit.RJUST = 0x0;//14,13
McbspaRegs.SPCR1.bit.CLKSTP = 0x0;//12,11
McbspaRegs.SPCR1.bit.rsvd = 0x0;//10,9,8
McbspaRegs.SPCR1.bit.DXENA = 0x0;//7
McbspaRegs.SPCR1.bit.ABIS = 0x0;//6
McbspaRegs.SPCR1.bit.RINTM = 0x0;//5,4
McbspaRegs.SPCR1.bit.RSYNCERR = 0x0;//3
McbspaRegs.SPCR1.bit.RFULL = 0x0;//2
McbspaRegs.SPCR1.bit.RRDY = 0x0;//1
McbspaRegs.SPCR1.bit.RRST = 0x0;//0
// McbspaRegs.RCR2.all=0x0000;
McbspaRegs.RCR2.bit.RPHASE = 0x0;//15
McbspaRegs.RCR2.bit.RFRLEN2 = 0x0;//14,13,12,11,10,9,8
McbspaRegs.RCR2.bit.RWDLEN2 = 0x0;//7,6,5
McbspaRegs.RCR2.bit.RCOMPAND = 0x0;//4,3
McbspaRegs.RCR2.bit.RFIG = 0x0;//2
McbspaRegs.RCR2.bit.RDATDLY = 0x0;//1,0
// McbspaRegs.RCR1.all=0x0000;
McbspaRegs.RCR1.bit.rsvd2 = 0x0;//15
McbspaRegs.RCR1.bit.RFRLEN1 = 0x0;//14,13,12,11,10,9,8
McbspaRegs.RCR1.bit.RWDLEN1 = 0x0;//7,6,5
McbspaRegs.RCR1.bit.rsvd1 = 0x0;//4,3,2,1,0
// McbspaRegs.XCR2.all=0x0000;
McbspaRegs.XCR2.bit.XPHASE = 0x0;//15
McbspaRegs.XCR2.bit.XFRLEN2 = 0x0;//14,13,12,11,10,9,8
McbspaRegs.XCR2.bit.XWDLEN2 = 0x0;//7,6,5
McbspaRegs.XCR2.bit.XCOMPAND = 0x0;//4,3
McbspaRegs.XCR2.bit.XFIG = 0x0;//2
McbspaRegs.XCR2.bit.XDATDLY = 0x0;//1,0
// McbspaRegs.XCR1.all=0x0000;
McbspaRegs.XCR1.bit.rsvd1 = 0x0;//15
McbspaRegs.XCR1.bit.XFRLEN1 = 0x0;//14,13,12,11,10,9,8
McbspaRegs.XCR1.bit.XWDLEN1 = 0x0;//7,6,5
McbspaRegs.XCR1.bit.rsvd2 = 0x0;//4,3,2,1,0
// McbspaRegs.SRGR2.all=0x20FF;
McbspaRegs.SRGR2.bit.GSYNC = 0x0;//15
McbspaRegs.SRGR2.bit.rsvd = 0x0;//14
McbspaRegs.SRGR2.bit.CLKSM = 0x1;//13
McbspaRegs.SRGR2.bit.FSGM = 0x0;//12
McbspaRegs.SRGR2.bit.FPER = 0x0;//11,10,9,8,7,6,5,4,3,2,1,0
// McbspaRegs.SRGR1.all=0x00FF;
McbspaRegs.SRGR1.bit.FWID = 0xFF;//15,14,13,12,11,10,9,8
McbspaRegs.SRGR1.bit.CLKGDV = 0x0;//7,6,5,4,3,2,1,0
// McbspaRegs.MCR2.all=0x0;
McbspaRegs.MCR2.bit.rsvd = 0x0;//15,14,13,12,11,10
McbspaRegs.MCR2.bit.XMCME = 0x0;//9
McbspaRegs.MCR2.bit.XPBBLK = 0x0;//8,7
McbspaRegs.MCR2.bit.XPABLK = 0x0;//6,5
McbspaRegs.MCR2.bit.XCBLK = 0x0;//4,3,2
McbspaRegs.MCR2.bit.XMCM = 0x0;//1,0
// McbspaRegs.MCR1.all=0x0;
McbspaRegs.MCR1.bit.rsvd = 0x0;//15,14,13,12,11,10
McbspaRegs.MCR1.bit.RMCME = 0x0;//9
McbspaRegs.MCR1.bit.RPBBLK = 0x0;//8,7
McbspaRegs.MCR1.bit.RPABLK = 0x0;//6,5
McbspaRegs.MCR1.bit.RCBLK = 0x0;//4,3,2
McbspaRegs.MCR1.bit.rsvd1 = 0x0;//1
McbspaRegs.MCR1.bit.RMCM = 0x0;//0
// McbspaRegs.PCR.all=0x0a00;
McbspaRegs.PCR.bit.rsvd = 0x0;//15,14,13,12
McbspaRegs.PCR.bit.FSXM = 0x1;//11
McbspaRegs.PCR.bit.FSRM = 0x0;//10
McbspaRegs.PCR.bit.CLKXM = 0x1;//9
McbspaRegs.PCR.bit.CLKRM = 0x0;//8
McbspaRegs.PCR.bit.SCLKME = 0x0;//7
McbspaRegs.PCR.bit.DX_STAT = 0x0;//5
McbspaRegs.PCR.bit.DR_STAT = 0x0;//4
McbspaRegs.PCR.bit.FSXP = 0x0;//3
McbspaRegs.PCR.bit.FSRP = 0x0;//2
McbspaRegs.PCR.bit.CLKXP = 0x0;//1
McbspaRegs.PCR.bit.CLKRP = 0x0;//0
}
void init_mcbsp_16bitspi(void)
{
/*
CLKSTP CLOCK SCHEME
0b00 CLOCK STOP MODE DISABLED. CLOCK ENABLED FOR NON SPI MODE
0b01 CLOCK STOP MODE DISABLED. CLOCK ENABLED FOR NON SPI MODE
0b10 LOW INACTIVE STATE WITHOUT DELAY.
ob11 LOW INACTIVE STATE WITH DELAY
*/
McbspaRegs.SPCR1.bit.CLKSTP = 0x2; //Enable Clock Stop Mode
/*
CLKXP = 0 => CLKX is positive
CLKXP = 1 => CLKX is negative
*/
McbspaRegs.PCR.bit.CLKXP = 0x0; //This bit determines
the polarity of the CLKX signal
/*
CLKRP = 0 => CLKR is positive
CLKRP = 1 => CLKR is negative
*/
McbspaRegs.PCR.bit.CLKRP = 0x0; //This bit determines
the polarity of the CLKR signal
/*
CLKXM = 0 => Device is Slave
CLKXM = 1 => Device is Master
*/
McbspaRegs.PCR.bit.CLKXM = 0x1; //This bit determines
whether CLKX is an input signal (Slave) or an output signal (Master)
/*
You must use a single phase frame (XPHASE = 0)
*/
McbspaRegs.XCR2.bit.XPHASE = 0x0; //This bit
determines the frame, whether it is single phase frame or dual phase
frame.
/*
You must use a single phase frame (RPHASE = 0)
*/
McbspaRegs.RCR2.bit.RPHASE = 0x0; //This bit
determines the frame, whether it is single phase frame or dual phase
frame.
/*
You must use a transmit frame length of 1 serial word length
*/
McbspaRegs.XCR1.bit.XFRLEN1 = 0x0; //This bit
determines the transmit frame length
/*
You must use a receive frame length of 1 serial word length
*/
McbspaRegs.RCR1.bit.RFRLEN1 = 0x0; //This bit
determines the receive frame length
/*
RWDLEN1 Receive word length
000 8
001 12
010 16
011 20
100 24
101 32
110 Reserved
111 Reserved
*/
McbspaRegs.RCR1.bit.RWDLEN1 = 0x2; // 16-bit word
/*
XWDLEN1 Transmit word length
000 8
001 12
010 16
011 20
100 24
101 32
110 Reserved
111 Reserved
*/
McbspaRegs.XCR1.bit.XWDLEN1 = 0x2; // 16-bit word
/*
SCLKME CLKSM
0 0 Reserved
0 1 LSPCLK
1 0 External CLKR pin Clock
1 1 External CLKX pin Clock
*/
McbspaRegs.PCR.bit.SCLKME = 0x0; //LSPCLK Setting
McbspaRegs.SRGR2.bit.CLKSM = 0x1; //LSPCLK Setting
/*
CLKGDV defines the divide down value for CLKG
00000000 - 1
00000001 - 2
00000010 - 3
.
.
.
11111111 - 256
*/
McbspaRegs.SRGR1.bit.CLKGDV = 0xFF;
/*
FSX
0 Frame synchronization pulses generated by an external
device.
FSR is an input pin
1 Frame synchronization generated internally by sample
rate generator.
FSR is an output pin except when GSYNC = 1 in SRGR.
*/
McbspaRegs.PCR.bit.FSXM = 0x1; //The FSX pin
is an output driven according to the FSGM bit
/*
0 Transmit frame sync signal (FSX) due to DXR(1/2)-to-XSR(1/2)
copy.
1 Transmit frame sync signal driven by the sample rate
generator frame sync
signal, FSG. TDM serial port control register (TSPC):TXM bit
*/
McbspaRegs.SRGR2.bit.FSGM = 0x0; //The
transmitter drives the frame sync pulse on the FSX pin every
//data is copied from
DXR1 to XSR1
McbspaRegs.PCR.bit.FSXP = 0x1; //FSX pin is active
low
McbspaRegs.XCR2.bit.XDATDLY = 0x1;
McbspaRegs.RCR2.bit.RDATDLY = 0x1;
McbspaRegs.SPCR2.bit.GRST = 0x1;
delay_loop();
McbspaRegs.SPCR2.bit.XRST = 0x1; // enable XRST/RRST
McbspaRegs.SPCR1.bit.RRST = 0x1;
McbspaRegs.SPCR2.bit.FRST = 0x1;
delay_loop();
McbspaRegs.SPCR2.all |=0x00C0; // Only enable FRST,GRST
}
void mcbsp_xmit(int a, int b)
{
McbspaRegs.DXR2.all=b;
McbspaRegs.DXR1.all=a;
}
void delay_loop()
{
long i;
for (i = 0; i < 1000000; i++) {}
}
void error(void)
{
asm(" ESTOP0"); // test failed!! Stop!
for (;;);
}
/******************************************************************************************/
Regards,
OST
