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;THIS IS THE SIMPLE I/O PROGRAM WHICH CAN SHOW DELAYED DATA .start ".data" ,0X809802 .sect ".data" .ENTRY START IN_ADDR .WORD 80804AH ;INPUT PORT ADDR OUT_ADDR .WORD 80804CH ;OUTPUT PORT ADDR SPORT .WORD 808040H ;SERIAL-PORT GLOBAL CONTROL REG ADDRESS SPRESET .WORD 02800344H ;SERIAL-PORT RESET SGCCTRL .WORD 0E800344H ;SERIAL-PORT GLOBAL CONTROL CONTROL REG SXCTRL .WORD 00000333H ;SERIAL-PORT TX PORT CONTROL REG STCTRL .WORD 0000000FH ;SERIAL-PORT TIMER CONTROL REG STPERIOD .WORD 00000002H ;SERIAL-PORT TIMER PERIOD RESET .WORD 0H ;SERIAL-PORT TIMER RESET VALUE SRCTRL .WORD 00000111H ;SERIAL-PORT RX PORT CONTROL REG STACKS .WORD 00809F00H START LDP RESET ;LOAD DATA PAGE POINTER ANDN 10H,IE ;DISABLE SERIAL-PORT TX INTERRUPT TO CPU LDI @STACKS,SP LDI SP,R1 MAIN LDI @SPORT,AR3 LDI @RESET,R0 LDI 4,IR0 STI R0,*+AR3(IR0) ;SERIAL-PORT TIMER RESET LDI @SPRESET,R0 STI R0,*AR3 ;SERIAL-PORT RESET LDI @SXCTRL,R0 STI R0,*+AR3(2) ;SERIAL-PORT TX CONTROL REG SET LDI @SRCTRL,R0 STI R0,*+AR3(3) ;SERIAL-PORT RX CONTROL REG SET LDI @STPERIOD,R0 STI R0,*+AR3(6) ;SERIAL-PORT TIMER PERIOD SET LDI @STCTRL,R0 STI R0,*+AR3(4) ;SERIAL-PORT TIMER CONTROL REG SET LDI @SGCCTRL,R0 STI R0,*AR3 ;SERIAL-PORT GLOBAL CONTROL REG SET BEGIN LDP IN_ADDR ;INIT DATA PAGE (0) LDI @IN_ADDR,AR5 ;INPUT PORT ADDR -> AR5404Ch LDI @OUT_ADDR,AR6 ;OUTPUT PORT ADDR-> AR64048h LOOP LDI *AR5,R1 ;INPUT FROM INPUT ADDR STI R1,*AR6 ;OUTPUT FROM OUTPUT ADDR B LOOP ;BRANCH BACK .END ;END Does anyone know the problem of this program .When the input signal come to the DR,FSR and CLKR.The output signal is not the same as the input signal come from the DSP in DX ,FSX and CLKX.It can not be direct input to direct output If you know what problem is ,please E-mail to me ,Thx |
The problem of simple I/O program
Started by ●December 28, 2000
