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Hello, This is possably OF but I am looking to interface a SDRAM DIMM or a DRAM component to a TMS320C32. Does anyone know of any resources or examples that they could share with me? Thanks in advance, Daren |
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DRAM
Started by ●June 22, 2001
Reply by ●June 23, 20012001-06-23
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At 12:53 PM 6/22/01, you wrote: >Hello, > This is possably OF but I am looking to interface a SDRAM DIMM or a >DRAM component to a TMS320C32. Does anyone know of any resources or >examples that they could share with me? >Thanks in advance, >Daren This is not an overly difficult design, but it is very inefficient. SDRAM will run with a very quick clock, but requires many (4 or more) clocks to retrieve data. SDRAM tends to work best in situations where blocks of memory need to be moved, such as in filling a cache line. So you can do two things. You can design a CPLD or FPGA based SDRAM controller to perform one read for every DSP read which will require that you use wait states to hold off the DSP. Or you can design a DMA based controller to move data between SDRAM and your faster RAM. If you need help with this, please contact me directly. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX |
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Reply by ●June 25, 20012001-06-25
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Daren- Or you can move from C3x processors, which are essentially obsolete, to C67xx processors which have built-in SDRAM controller. Glueless interface plus reasonably efficient; see the DSK C6711 schematic published by TI for an example. Jeff Brower Signalogic On Fri, 22 Jun 2001, Rick Collins <> wrote: >At 12:53 PM 6/22/01, you wrote: >>Hello, >> This is possably OF but I am looking to interface a SDRAM DIMM or a >>DRAM component to a TMS320C32. Does anyone know of any resources or >>examples that they could share with me? >>Thanks in advance, >>Daren > >This is not an overly difficult design, but it is very inefficient. SDRAM >will run with a very quick clock, but requires many (4 or more) clocks to >retrieve data. SDRAM tends to work best in situations where blocks of >memory need to be moved, such as in filling a cache line. > >So you can do two things. You can design a CPLD or FPGA based SDRAM >controller to perform one read for every DSP read which will require that >you use wait states to hold off the DSP. Or you can design a DMA based >controller to move data between SDRAM and your faster RAM. > >If you need help with this, please contact me directly. > >Rick Collins >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design URL http://www.arius.com >4 King Ave 301-682-7772 Voice >Frederick, MD 21701-3110 301-682-7666 FAX |
Reply by ●June 25, 20012001-06-25
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Hi Daren Rick is right about the SDRAM pipeline being pretty long. For more generic DRAM designs you might find these application notes from the TI web page to be helpful. Like most everything on our lamo web page I had trouble finding them. You have to enter 'EDRAM controller' and not 'DRAM controller'. I just happened to have the SPRA number (like thats any good to anyone else) written down. SPRA290 EDRAM CONTROLLER FOR THE 60MHZ TMS320C40 DSP SPRA172 EDRAM MEMORY CONTROLLER FOR THE TMS320C31 DSP Another possability would be Synchronous Burst SRAM. These devices have considerably shorter pipelines (1 for flow through and 2 cycles for pipelined) and therefor faster for reading and writing. Though I have not built a system using one of these devices the logic looks fairly compatible and the addressing is linear so you dont have to build a RAS/CAS selector. The design seems like it would be little more than inverting R/W and running with 1-2 wait states. The only shortfall I see is that the density of these devices has not kept pace with other DRAM technology even though at least some are built from DRAMs on the inside (see www.mosys.com). The other SBSRAM I have looked at is from Micron but I cant tell from the documentation what technology is used. Hope this helps, Keith Larson PS: One other thing to watch for is that most if not all of the newer DRAMs have 3V IO. For this reason you may also want to look into the TMS320VC33. ------------ At 09:09 PM 6/22/01 -0400, you wrote: At 12:53 PM 6/22/01, you wrote: Hello, This is possably OF but I am looking to interface a SDRAM DIMM or a DRAM component to a TMS320C32. Does anyone know of any resources or examples that they could share with me? Thanks in advance, Daren ---------------- This is not an overly difficult design, but it is very inefficient. SDRAM will run with a very quick clock, but requires many (4 or more) clocks to retrieve data. SDRAM tends to work best in situations where blocks of memory need to be moved, such as in filling a cache line. So you can do two things. You can design a CPLD or FPGA based SDRAM controller to perform one read for every DSP read which will require that you use wait states to hold off the DSP. Or you can design a DMA based controller to move data between SDRAM and your faster RAM. If you need help with this, please contact me directly. Rick Collins Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX ____________________________________ Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. _____________________________________ About this discussion group: To Join: Send an email to To Post: Send an email to To Leave: Send an email to Archives: http://groups.yahoo.com/group/c3x More Groups: http://www.dsprelated.com ">http://docs.yahoo.com/info/terms/ |
