Another MCBSP question (signals)

Started by Krunoslav Sekovanic October 29, 2003

I tried to configure C5402 to generate this kind of clk/frm signals:

clk: -_-_-_-_-_-_
frm: ______--____
data _______xxxxx
(hope it's visible; if not, please copy to fixed width font capable
txt editor)

- frm pulse width is 1 clk period,
- clk falls in the middle of frm=1
- 1st data bit starts (MSB first) with falling clk, which is in the
middle of frm pulse

I cold not find any such options in MCBSP registers to generate this
situation, or are there any (to start tx-data in the center of active
frm)? How does MCBSP receive such configured data? (misses frm?)

ThanQ very much!
Krunoslav Sekovanic