Clarification

Hi All,

I am sending a pdf of an LDO preferred by TI.
In page 10 the reset outputs of the device are ANDed and output of this is PG.
What is this PG i am not getting that. NO info is given about that.

Moreover one of the reset (1RESET) is 3.3V and other(2RESET) is 1.9V.
Actually what is the need of 1.9V reset for a processor??

I would be glad if any one helps me in this regard.

Regards,

---------------------------------
It's here! Your new message!
Get new email alerts with the free Yahoo! Toolbar. Start a New Thread

Prathyush-

> I am sending a pdf of an LDO preferred by TI.
> In page 10 the reset outputs of the device are ANDed and output of this is PG.
> What is this PG i am not getting that. NO info is given about that.
>
> Moreover one of the reset (1RESET) is 3.3V and other(2RESET) is 1.9V.
> Actually what is the need of 1.9V reset for a processor??

I don't have time to look over the PDF, but my guess would be that TI is suggesting
that you AND the two LDO "output good" signals together and combine (another AND)
with the DSP Reset signal (typically active low). The idea being that the device is
held in reset at least long enough for both power rails (Vcc IO and Vcc core) to
reach valid levels. Of course you may have to hold Reset longer depending on what
else is happening on your board, for example wait until oscillator input is
stabilized, config R signals are valid, etc.

-Jeff Start a New Thread