I all,
I'm reading this DSP's Data Manual (Literature Number: SPRS180C) and
I
see that it has
- ON CHIP registers from address 0x00 to 0x1F
- Pheriperals Memory Mapped Registers from 0x20 to 0x5F
What I don't understand is the "sub addressing" method used to access
the registers..
In particular, with reference to the Data Manual, I can't figure out the
addressing in Table 3-3.
Texas Instruments puts the register definitions into this code
:
in particular I can't identify what a line such as
MCBSP_SUBREG_WRITE(1, SPCR1_SUBADDR, 0x0001); // enable rx
is exactly doing... can you help me out ???
Thanks in advance...
C5471 Registers addressing
Started by ●April 20, 2008
Reply by ●April 24, 20082008-04-24
Inuy-
> I'm reading this DSP's Data Manual (Literature Number: SPRS180C) and I
> see that it has
> - ON CHIP registers from address 0x00 to 0x1F
> - Pheriperals Memory Mapped Registers from 0x20 to 0x5F
> What I don't understand is the "sub addressing" method used to access
> the registers..
For some C54xx devices, TI used a sub-addressing scheme to access some McBSP, DMA,
and other peripheral registers. The purpose of this scheme is to allow a large
number of registers to be mapped into a small memory space.
In other words, the C54xx architecture was running out of possible "reserved address
space" for onchip registers, and to add more would have impacted other things that TI
didn't want to change. So they implemented sub-addressing. On other processor
devices, this type of scheme has historically been called "page mode" or "bank"
addressing.
> In particular, with reference to the Data Manual, I can't figure out the
> addressing in Table 3-3.
> Texas Instruments puts the register definitions into this code
> :
> in particular I can't identify what a line such as
>
> MCBSP_SUBREG_WRITE(1, SPCR1_SUBADDR, 0x0001); // enable rx
> is exactly doing... can you help me out ???
If you look into the source code for the above function, you might see something
like:
void McBSP_Subreg_Write(UINT Port, UINT SubAddr, UINT Value) {
*(UINT*)BaseAddr[Port] = SubAddr;
*(UINT*)DataAddr[Port] = Value;
}
The above lines are just pseudo-code. But they illustrate the key point -- the
sub-addressing scheme requires TWO writes: the first one to set the "currently
active" sub-register, and the second one to actually write the register value.
I hope that makes sense.
-Jeff
> I'm reading this DSP's Data Manual (Literature Number: SPRS180C) and I
> see that it has
> - ON CHIP registers from address 0x00 to 0x1F
> - Pheriperals Memory Mapped Registers from 0x20 to 0x5F
> What I don't understand is the "sub addressing" method used to access
> the registers..
For some C54xx devices, TI used a sub-addressing scheme to access some McBSP, DMA,
and other peripheral registers. The purpose of this scheme is to allow a large
number of registers to be mapped into a small memory space.
In other words, the C54xx architecture was running out of possible "reserved address
space" for onchip registers, and to add more would have impacted other things that TI
didn't want to change. So they implemented sub-addressing. On other processor
devices, this type of scheme has historically been called "page mode" or "bank"
addressing.
> In particular, with reference to the Data Manual, I can't figure out the
> addressing in Table 3-3.
> Texas Instruments puts the register definitions into this code
> :
> in particular I can't identify what a line such as
>
> MCBSP_SUBREG_WRITE(1, SPCR1_SUBADDR, 0x0001); // enable rx
> is exactly doing... can you help me out ???
If you look into the source code for the above function, you might see something
like:
void McBSP_Subreg_Write(UINT Port, UINT SubAddr, UINT Value) {
*(UINT*)BaseAddr[Port] = SubAddr;
*(UINT*)DataAddr[Port] = Value;
}
The above lines are just pseudo-code. But they illustrate the key point -- the
sub-addressing scheme requires TWO writes: the first one to set the "currently
active" sub-register, and the second one to actually write the register value.
I hope that makes sense.
-Jeff
