Forums

PLL config problem

Started by thed...@yahoo.com October 1, 2008
I'm using CCSv3.1 and the C5416. I attempted to configure the PLL module using the CSL GUI, and upon compiling, I get the following errors.

"C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "BSCR" is undefined
"C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "DIVFCT" is undefined
"C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "BSCR" is undefined
"C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "DIVFCT" is undefined

Anyone experience this before?
Dr-

> I'm using CCSv3.1 and the C5416. I attempted to configure the PLL module
> using the CSL GUI, and upon compiling, I get the following errors.
>
> "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "BSCR" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "DIVFCT" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "BSCR" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "DIVFCT" is undefined
>
> Anyone experience this before?

Did you define CHIP_5416? if you are not using DSP/BIOS (which I recall that you're
not), then you have to manually define the chip type for CSL purposes. You can do
this under Project | Build Options | Preprocessor | Define Symbols.

Also, did you see this page:

http://c5000.spectrumdigital.com/pep5416/docs/bsp/bsl.html

which would apply to the PEP5416 board that you are using.

-Jeff
Jeff,

I am using DSP/BIOS and had the chip defined before when I wasn't using it. At this point, I don't think the GUI for the PLL config is necessary. I looked at the pin assignments for the clock mode register and set the multiplier that I wanted to use, which should be sufficient. TI support claimed it might be an old unstable GUI that I'm using, though it doesn't really matter anymore.

The reason I wanted to try the graphical configuration is because something isn't making sense in my program. When using the lines

while(1)
{
while (!PEP5416_AIC23_read16(hCodec, &buffer[i]));
while (!PEP5416_AIC23_write16(hCodec, buffer[i]));
PEP5416_waitu(t)
}

I varied t until the output started to become distorted to see if this "breaking time" corresponds to the AIC23 sampling rate, which it didn't (it measured 10 usec with an AIC sample rate of 12kHz). I then suspected that I might not be setting my clock speeds properly, which I don't think is the case now, since I used PEP5416_setFreq( Fs ). Perhaps there is more to the PEP5416_waitu( ) function than I realize.

----- Original Message ----
From: Jeff Brower
To: t...@yahoo.com
Cc: c...
Sent: Thursday, October 2, 2008 1:19:38 PM
Subject: Re: [c54x] PLL config problem

Dr-

> I'm using CCSv3.1 and the C5416. I attempted to configure the PLL module
> using the CSL GUI, and upon compiling, I get the following errors.
>
> "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "BSCR" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "DIVFCT" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "BSCR" is undefined
> "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "DIVFCT" is undefined
>
> Anyone experience this before?

Did you define CHIP_5416? if you are not using DSP/BIOS (which I recall that you're
not), then you have to manually define the chip type for CSL purposes. You can do
this under Project | Build Options | Preprocessor | Define Symbols.

Also, did you see this page:

http://c5000.spectrumdigital.com/pep5416/docs/bsp/bsl.html

which would apply to the PEP5416 board that you are using.

-Jeff
Hi Steve-
> I am using DSP/BIOS and had the chip defined before when I wasn't using it.
>
Ok, so DSP/BIOS is in the picture now. That will be good in the long-run.
> At this point, I don't think the GUI for the PLL config is necessary. I looked at
> the pin assignments for the clock mode register and set the multiplier that I
> wanted to use, which should be sufficient. TI support claimed it might be an old
> unstable GUI that I'm using, though it doesn't really matter anymore.
>
Well TI support likes to run from CCS v3.1. Anything less than v3.3 makes it easier
for them to say "please upgrade" instead of dealing with the actual question. If it
continues to show in v3.3 then they will be helpful.
> The reason I wanted to try the graphical configuration is because something isn't
> making sense in my program. When using the lines
>
> while(1)
> {
> while (!PEP5416_AIC23_read16(hCodec, &buffer[i]));
> while (!PEP5416_AIC23_write16(hCodec, buffer[i]));
> PEP5416_waitu(t)
> }
>
> I varied t until the output started to become distorted to see if this "breaking
> time" corresponds to the AIC23 sampling rate, which it didn't (it measured 10 usec
> with an AIC sample rate of 12kHz). I then suspected that I might not be setting my
> clock speeds properly, which I don't think is the case now, since I used
> PEP5416_setFreq( Fs ). Perhaps there is more to the PEP5416_waitu( ) function than
> I realize.
>
You can independently verify the sampling rate by putting some audio tones through
your AIC23 loopback -- for example put in a 5.5 or 6 kHz tone and listen to what you
get out. It should be a) audible if Fs is correct, and b) identical to the input if
loopback is working correctly without glitch or buffering issues.

All the functions you list will take finite processing time that eats into your
sample time. But using up 73 usec doesn't make sense for simple C code functions.
Are you sure that Fs can be set continuously on the PEP5416 board and doesn't have
discrete settings such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your
empirical value for waitu() would make sense.

-Jeff
> ----- Original Message ----
> From: Jeff Brower
> To: t...@yahoo.com
> Cc: c...
> Sent: Thursday, October 2, 2008 1:19:38 PM
> Subject: Re: [c54x] PLL config problem
>
> Dr-
>
> > I'm using CCSv3.1 and the C5416. I attempted to configure the PLL module
> > using the CSL GUI, and upon compiling, I get the following errors.
> >
> > "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "BSCR" is
> undefined
> > "C:/ti/C5400/csl/include/csl_pll.h", line 187: error: identifier "DIVFCT" is
> undefined
> > "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "BSCR" is
> undefined
> > "C:/ti/C5400/csl/include/csl_pll.h", line 225: error: identifier "DIVFCT" is
> undefined
> >
> > Anyone experience this before?
>
> Did you define CHIP_5416? if you are not using DSP/BIOS (which I recall that
> you're
> not), then you have to manually define the chip type for CSL purposes. You can do
> this under Project | Build Options | Preprocessor | Define Symbols.
>
> Also, did you see this page:
>
> http://c5000.spectrumdigital.com/pep5416/docs/bsp/bsl.html
>
> which would apply to the PEP5416 board that you are using.
>
> -Jeff
>
Steve-
> The AIC23 does have discrete settings that include 96, 48, 24, 16, 12, and 8 kHz.
> I lowered the sample rate to allow more time for processing between reading and
> writing samples. Even if I entered an invalid frequency, by default, the sampling
> rate would be set to 48 kHz, and the value of 10 usec would still not make sense.
> I know that the AIC23_setFreq command is changing the sample rate, because I varied
> the wait time for other sample rates, and it changed (though didn't make sense for
> the other sample rates). Perhaps to rectify this situation, I'll directly set the
> bits in the AIC clock register to achieve the desired sampling rate and then
> experiment with tones rather than a software spin delay. Thanks for the
> suggestion.
>
Another suggestion would be to set up Timer1 (not used by DSP/BIOS) and count clock
cycles before and after the PEP5416_AIC23_xx() calls. Then you would know exactly
how much time is being used, and how long PEP5416_waitu() is actually waiting. One
or more of these functions is the 'culprit' and you need a way to find out.

-Jeff
> ----- Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c...
> Sent: Thursday, October 2, 2008 6:36:20 PM
> Subject: Re: [c54x] PLL config problem
>
> Hi Steve-
>> I am using DSP/BIOS and had the chip defined before when I wasn't using it.
>>
> Ok, so DSP/BIOS is in the picture now. That will be good in the long-run.
>> At this point, I don't think the GUI for the PLL config is necessary. I looked
>> at the pin assignments for the clock mode register and set the multiplier that I
>> wanted to use, which should be sufficient. TI support claimed it might be an old
>> unstable GUI that I'm using, though it doesn't really matter anymore.
>>
> Well TI support likes to run from CCS v3.1. Anything less than v3.3 makes it
> easier for them to say "please upgrade" instead of dealing with the actual
> question. If it continues to show in v3.3 then they will be helpful.
>> The reason I wanted to try the graphical configuration is because something isn't
>> making sense in my program. When using the lines
>>
>> while(1)
>> {
>> while (!PEP5416_AIC23_ read16(hCodec, &buffer[i]));
>> while (!PEP5416_AIC23_ write16(hCodec, buffer[i]));
>> PEP5416_waitu( t)
>> }
>>
>> I varied t until the output started to become distorted to see if this "breaking
>> time" corresponds to the AIC23 sampling rate, which it didn't (it measured 10
>> usec with an AIC sample rate of 12kHz). I then suspected that I might not be
>> setting my clock speeds properly, which I don't think is the case now, since I
>> used PEP5416_setFreq( Fs ). Perhaps there is more to the PEP5416_waitu( )
>> function than I realize.
>>
> You can independently verify the sampling rate by putting some audio tones through
> your AIC23 loopback -- for example put in a 5.5 or 6 kHz tone and listen to what
> you get out. It should be a) audible if Fs is correct, and b) identical to the
> input if loopback is working correctly without glitch or buffering issues.
>
> All the functions you list will take finite processing time that eats into your
> sample time. But using up 73 usec doesn't make sense for simple C code functions.
> Are you sure that Fs can be set continuously on the PEP5416 board and doesn't have
> discrete settings such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your
> empirical value for waitu() would make sense.
>
> -Jeff
>> ----- Original Message ----
>> From: Jeff Brower
>> To: thedoctor152003@ yahoo.com
>> Cc: c54x@yahoogroups. com
>> Sent: Thursday, October 2, 2008 1:19:38 PM
>> Subject: Re: [c54x] PLL config problem
>>
>> Dr-
>>
>> > I'm using CCSv3.1 and the C5416. I attempted to configure the PLL module
>> > using the CSL GUI, and upon compiling, I get the following errors.
>> >
>> > "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187: error: identifier "BSCR" is
>> undefined
>> > "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187: error: identifier "DIVFCT" is
>> undefined
>> > "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225: error: identifier "BSCR" is
>> undefined
>> > "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225: error: identifier "DIVFCT" is
>> undefined
>> >
>> > Anyone experience this before?
>>
>> Did you define CHIP_5416? if you are not using DSP/BIOS (which I recall that
>> you're
>> not), then you have to manually define the chip type for CSL purposes. You can
>> do
>> this under Project | Build Options | Preprocessor | Define Symbols.
>>
>> Also, did you see this page:
>>
>> http://c5000. spectrumdigital. com/pep5416/ docs/bsp/ bsl.html
>>
>> which would apply to the PEP5416 board that you are using.
>>
>> -Jeff
>>
Ok, that's sounds reasonable. I'm going to have to configure a timer to control a recurring interrupt anyway so that the sample rate of the program's filters is met, at least once I get code running in reasonable amounts of time.

Just a quick word on McBSP + DMA. When you speak of using the two together, do you mean using a ping-pong buffering scheme while using DMA channel sorting?

----- Original Message ----
From: Jeff Brower
To: Steve Baker
Cc: c...
Sent: Friday, October 3, 2008 4:28:02 PM
Subject: Re: [c54x] PLL config problem
Steve-

The
AIC23 does have discrete settings that include 96, 48, 24, 16, 12, and
8 kHz. I lowered the sample rate to allow more time for processing
between reading and writing samples. Even if I entered an invalid
frequency, by default, the sampling rate would be set to 48 kHz, and the
value of 10 usec would still not make sense. I know that the AIC23_setFreq
command is changing the sample rate, because I varied the wait time for
other sample rates, and it changed (though didn't make sense for the other
sample rates). Perhaps to rectify this situation, I'll directly set
the bits in the AIC clock register to achieve the desired sampling rate
and then experiment with tones rather than a software spin delay.
Thanks for the suggestion.
Another suggestion would be to set up Timer1 (not
used by DSP/BIOS) and count clock cycles before and after the PEP5416_AIC23_ xx()
calls. Then you would know exactly how much time is being used, and
how long PEP5416_waitu( ) is actually waiting. One or more of these
functions is the 'culprit' and you need a way to find out.
-Jeff

-----
Original Message ----
From: Jeff Brower
To: Steve Baker
Cc: c54x@yahoogroups. com
Sent: Thursday, October 2, 2008 6:36:20 PM
Subject: Re: [c54x] PLL config problem

Hi Steve-

I
am using DSP/BIOS and had the chip defined before when I wasn't using it.Ok, so DSP/BIOS is in the picture now. That will
be good in the long-run.

At
this point, I don't think the GUI for the PLL config is necessary.
I looked at the pin assignments for the clock mode register and set the
multiplier that I wanted to use, which should be sufficient. TI support
claimed it might be an old unstable GUI that I'm using, though it doesn't
really matter anymore.Well TI support likes to run from CCS v3.1. Anything
less than v3.3 makes it easier for them to say "please upgrade" instead
of dealing with the actual question. If it continues to show in v3.3
then they will be helpful.

The
reason I wanted to try the graphical configuration is because something
isn't making sense in my program. When using the lines
while(1)
{

while (!PEP5416_AIC23_ read16(hCodec, &buffer[i]));

while (!PEP5416_AIC23_ write16(hCodec, buffer[i]));

PEP5416_waitu( t)
}
I varied t until the output started to become distorted
to see if this "breaking time" corresponds to the AIC23 sampling rate,
which it didn't (it measured 10 usec with an AIC sample rate of 12kHz).
I then suspected that I might not be setting my clock speeds properly,
which I don't think is the case now, since I used PEP5416_setFreq( Fs ).
Perhaps there is more to the PEP5416_waitu( ) function than I realize.You can independently verify the sampling rate by putting
some audio tones through your AIC23 loopback -- for example put in a 5.5
or 6 kHz tone and listen to what you get out. It should be a) audible
if Fs is correct, and b) identical to the input if loopback is working
correctly without glitch or buffering issues.
All the functions you list will take finite processing
time that eats into your sample time. But using up 73 usec doesn't
make sense for simple C code functions. Are you sure that Fs can
be set continuously on the PEP5416 board and doesn't have discrete settings
such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your empirical
value for waitu() would make sense.
-Jeff

-----
Original Message ----
From: Jeff Brower
To: thedoctor152003@ yahoo.com
Cc: c54x@yahoogroups. com
Sent: Thursday, October 2, 2008 1:19:38 PM
Subject: Re: [c54x] PLL config problem
Dr-
> I'm using CCSv3.1 and the C5416. I attempted
to configure the PLL module
> using the CSL GUI, and upon compiling, I get the
following errors.
>
> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
error: identifier "BSCR" is undefined
> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
error: identifier "DIVFCT" is undefined
> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
error: identifier "BSCR" is undefined
> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
error: identifier "DIVFCT" is undefined
>
> Anyone experience this before?
Did you define CHIP_5416? if you are not using
DSP/BIOS (which I recall that you're
not), then you have to manually define the chip type
for CSL purposes. You can do
this under Project | Build Options | Preprocessor
| Define Symbols.
Also, did you see this page:
http://c5000.
spectrumdigital. com/pep5416/ docs/bsp/ bsl.html
which would apply to the PEP5416 board that you are
using.
-Jeff
Steve-

> Ok, that's sounds reasonable. I'm going to have to configure
> a timer to control a recurring interrupt anyway so that
> the sample rate of the program's filters is met, at least
> once I get code running in reasonable amounts of time.

Can you explain that further? The sampling rate should be driven by the AIC23, which is in turn driving a McBSP,
which is in turn driving either interrupts directly or indirectly through DMA. Other clocks in the system might be
used for monitoring, code profiling / performance measurement, I/O interfaces for processing results, etc -- but would
not be used for sampling.

> Just a quick word on McBSP + DMA. When you speak of using
> the two together, do you mean using a ping-pong buffering
> scheme while using DMA channel sorting?

Typically, DMA fills up two ping-pong buffers, switching back and forth between them. Each time a buffer is filled a
DMA interrupt is triggered and your code responds. Your code should process the recently filled buffer (ping), while
DMA is filling the other buffer (pong). A second, separate pair of buffers is used for transmit (D/A).

-Jeff

> ----- Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c...
> Sent: Friday, October 3, 2008 4:28:02 PM
> Subject: Re: [c54x] PLL config problem
> Steve-
>
> The
> AIC23 does have discrete settings that include 96, 48, 24, 16, 12, and
> 8 kHz. I lowered the sample rate to allow more time for processing
> between reading and writing samples. Even if I entered an invalid
> frequency, by default, the sampling rate would be set to 48 kHz, and the
> value of 10 usec would still not make sense. I know that the AIC23_setFreq
> command is changing the sample rate, because I varied the wait time for
> other sample rates, and it changed (though didn't make sense for the other
> sample rates). Perhaps to rectify this situation, I'll directly set
> the bits in the AIC clock register to achieve the desired sampling rate
> and then experiment with tones rather than a software spin delay.
> Thanks for the suggestion.
> Another suggestion would be to set up Timer1 (not
> used by DSP/BIOS) and count clock cycles before and after the PEP5416_AIC23_ xx()
> calls. Then you would know exactly how much time is being used, and
> how long PEP5416_waitu( ) is actually waiting. One or more of these
> functions is the 'culprit' and you need a way to find out.
> -Jeff
>
> -----
> Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c54x@yahoogroups. com
> Sent: Thursday, October 2, 2008 6:36:20 PM
> Subject: Re: [c54x] PLL config problem
>
> Hi Steve-
>
> I
> am using DSP/BIOS and had the chip defined before when I wasn't using it.Ok, so DSP/BIOS is in the picture now. That
> will
> be good in the long-run.
>
> At
> this point, I don't think the GUI for the PLL config is necessary.
> I looked at the pin assignments for the clock mode register and set the
> multiplier that I wanted to use, which should be sufficient. TI support
> claimed it might be an old unstable GUI that I'm using, though it doesn't
> really matter anymore.Well TI support likes to run from CCS v3.1. Anything
> less than v3.3 makes it easier for them to say "please upgrade" instead
> of dealing with the actual question. If it continues to show in v3.3
> then they will be helpful.
>
> The
> reason I wanted to try the graphical configuration is because something
> isn't making sense in my program. When using the lines
> while(1)
> {
>
> while (!PEP5416_AIC23_ read16(hCodec, &buffer[i]));
>
> while (!PEP5416_AIC23_ write16(hCodec, buffer[i]));
>
> PEP5416_waitu( t)
> }
> I varied t until the output started to become distorted
> to see if this "breaking time" corresponds to the AIC23 sampling rate,
> which it didn't (it measured 10 usec with an AIC sample rate of 12kHz).
> I then suspected that I might not be setting my clock speeds properly,
> which I don't think is the case now, since I used PEP5416_setFreq( Fs ).
> Perhaps there is more to the PEP5416_waitu( ) function than I realize.You can independently verify the sampling rate
> by putting
> some audio tones through your AIC23 loopback -- for example put in a 5.5
> or 6 kHz tone and listen to what you get out. It should be a) audible
> if Fs is correct, and b) identical to the input if loopback is working
> correctly without glitch or buffering issues.
> All the functions you list will take finite processing
> time that eats into your sample time. But using up 73 usec doesn't
> make sense for simple C code functions. Are you sure that Fs can
> be set continuously on the PEP5416 board and doesn't have discrete settings
> such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your empirical
> value for waitu() would make sense.
> -Jeff
>
> -----
> Original Message ----
> From: Jeff Brower
> To: thedoctor152003@ yahoo.com
> Cc: c54x@yahoogroups. com
> Sent: Thursday, October 2, 2008 1:19:38 PM
> Subject: Re: [c54x] PLL config problem
> Dr-
>> I'm using CCSv3.1 and the C5416. I attempted
> to configure the PLL module
>> using the CSL GUI, and upon compiling, I get the
> following errors.
>>
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
> error: identifier "BSCR" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
> error: identifier "DIVFCT" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
> error: identifier "BSCR" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
> error: identifier "DIVFCT" is undefined
>>
>> Anyone experience this before?
> Did you define CHIP_5416? if you are not using
> DSP/BIOS (which I recall that you're
> not), then you have to manually define the chip type
> for CSL purposes. You can do
> this under Project | Build Options | Preprocessor
> | Define Symbols.
> Also, did you see this page:
> http://c5000.
> spectrumdigital. com/pep5416/ docs/bsp/ bsl.html
> which would apply to the PEP5416 board that you are
> using.
> -Jeff
Regarding the recurring interrupt I spoke of, perhaps I am a bit confused in that matter. The program I'm running utilizes filters designed for a sampling rate of 22050 Hz, which is a strict specification since the program is a simulator for a cochlear implant product. Since the AIC23 cannot operate at this frequency, I figured I would allow more time for processing than the 22.05 kHz would require, and then allow a timer of some sort to stop processing until the next sample rate period. The fact is that this recurring interrupt scheme was considered amongst my research group when single-sample processing was thought to be the way to go. As this is no longer the case, I must think about this concept further. I apologize for that. I more or less spoke (or rather typed) before I thought.

Steve

----- Original Message ----
From: Jeff Brower
To: Steve Baker
Cc: c...
Sent: Sunday, October 5, 2008 1:27:47 PM
Subject: Re: [c54x] PLL config problem
Steve-

> Ok, that's sounds reasonable. I'm going to have to configure
> a timer to control a recurring interrupt anyway so that
> the sample rate of the program's filters is met, at least
> once I get code running in reasonable amounts of time.

Can you explain that further? The sampling rate should be driven by the AIC23, which is in turn driving a McBSP,
which is in turn driving either interrupts directly or indirectly through DMA. Other clocks in the system might be
used for monitoring, code profiling / performance measurement, I/O interfaces for processing results, etc -- but would
not be used for sampling.

> Just a quick word on McBSP + DMA. When you speak of using
> the two together, do you mean using a ping-pong buffering
> scheme while using DMA channel sorting?

Typically, DMA fills up two ping-pong buffers, switching back and forth between them. Each time a buffer is filled a
DMA interrupt is triggered and your code responds. Your code should process the recently filled buffer (ping), while
DMA is filling the other buffer (pong). A second, separate pair of buffers is used for transmit (D/A).

-Jeff

> ----- Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c54x@yahoogroups. com
> Sent: Friday, October 3, 2008 4:28:02 PM
> Subject: Re: [c54x] PLL config problem
> Steve-
>
> The
> AIC23 does have discrete settings that include 96, 48, 24, 16, 12, and
> 8 kHz. I lowered the sample rate to allow more time for processing
> between reading and writing samples. Even if I entered an invalid
> frequency, by default, the sampling rate would be set to 48 kHz, and the
> value of 10 usec would still not make sense. I know that the AIC23_setFreq
> command is changing the sample rate, because I varied the wait time for
> other sample rates, and it changed (though didn't make sense for the other
> sample rates). Perhaps to rectify this situation, I'll directly set
> the bits in the AIC clock register to achieve the desired sampling rate
> and then experiment with tones rather than a software spin delay.
> Thanks for the suggestion.
> Another suggestion would be to set up Timer1 (not
> used by DSP/BIOS) and count clock cycles before and after the PEP5416_AIC23_ xx()
> calls. Then you would know exactly how much time is being used, and
> how long PEP5416_waitu( ) is actually waiting. One or more of these
> functions is the 'culprit' and you need a way to find out.
> -Jeff
>
> -----
> Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c54x@yahoogroups. com
> Sent: Thursday, October 2, 2008 6:36:20 PM
> Subject: Re: [c54x] PLL config problem
>
> Hi Steve-
>
> I
> am using DSP/BIOS and had the chip defined before when I wasn't using it.Ok, so DSP/BIOS is in the picture now. That
> will
> be good in the long-run.
>
> At
> this point, I don't think the GUI for the PLL config is necessary.
> I looked at the pin assignments for the clock mode register and set the
> multiplier that I wanted to use, which should be sufficient. TI support
> claimed it might be an old unstable GUI that I'm using, though it doesn't
> really matter anymore.Well TI support likes to run from CCS v3.1. Anything
> less than v3.3 makes it easier for them to say "please upgrade" instead
> of dealing with the actual question. If it continues to show in v3.3
> then they will be helpful.
>
> The
> reason I wanted to try the graphical configuration is because something
> isn't making sense in my program. When using the lines
> while(1)
> {
>
> while (!PEP5416_AIC23_ read16(hCodec, &buffer[i])) ;
>
> while (!PEP5416_AIC23_ write16(hCodec, buffer[i]));
>
> PEP5416_waitu( t)
> }
> I varied t until the output started to become distorted
> to see if this "breaking time" corresponds to the AIC23 sampling rate,
> which it didn't (it measured 10 usec with an AIC sample rate of 12kHz).
> I then suspected that I might not be setting my clock speeds properly,
> which I don't think is the case now, since I used PEP5416_setFreq( Fs ).
> Perhaps there is more to the PEP5416_waitu( ) function than I realize.You can independently verify the sampling rate
> by putting
> some audio tones through your AIC23 loopback -- for example put in a 5.5
> or 6 kHz tone and listen to what you get out. It should be a) audible
> if Fs is correct, and b) identical to the input if loopback is working
> correctly without glitch or buffering issues.
> All the functions you list will take finite processing
> time that eats into your sample time. But using up 73 usec doesn't
> make sense for simple C code functions. Are you sure that Fs can
> be set continuously on the PEP5416 board and doesn't have discrete settings
> such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your empirical
> value for waitu() would make sense.
> -Jeff
>
> -----
> Original Message ----
> From: Jeff Brower
> To: thedoctor152003@ yahoo.com
> Cc: c54x@yahoogroups. com
> Sent: Thursday, October 2, 2008 1:19:38 PM
> Subject: Re: [c54x] PLL config problem
> Dr-
>> I'm using CCSv3.1 and the C5416. I attempted
> to configure the PLL module
>> using the CSL GUI, and upon compiling, I get the
> following errors.
>>
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
> error: identifier "BSCR" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
> error: identifier "DIVFCT" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
> error: identifier "BSCR" is undefined
>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
> error: identifier "DIVFCT" is undefined
>>
>> Anyone experience this before?
> Did you define CHIP_5416? if you are not using
> DSP/BIOS (which I recall that you're
> not), then you have to manually define the chip type
> for CSL purposes. You can do
> this under Project | Build Options | Preprocessor
> | Define Symbols.
> Also, did you see this page:
> http://c5000.
> spectrumdigital. com/pep5416/ docs/bsp/ bsl.html
> which would apply to the PEP5416 board that you are
> using.
> -Jeff
Steve-

> Regarding the recurring interrupt I spoke of, perhaps I am a bit confused in that matter. The program I'm running
> utilizes filters designed for a sampling rate of 22050 Hz, which is a strict specification since the program is a
> simulator for a cochlear implant product. Since the AIC23 cannot operate at this frequency, I figured I would allow
> more time for processing than the 22.05 kHz would require, and then allow a timer of some sort to stop processing
> until the next sample rate period. The fact is that this recurring interrupt scheme was considered amongst my
> research group when single-sample processing was thought to be the way to go. As this is no longer the case, I must
> think about this concept further. I apologize for that. I more or less spoke (or rather typed) before I thought.
You wouldn't want to do that. It would add unnecessary software complexity, subtract valuable MIPS, and would look
"non standard" -- something for which you'd find it difficult to get vendor and peer support. Plus you might
introduce some "sample jitter", which could jeopardize the whole premise of linear time-invariant system on which your
speech processing is based.

A better approach is to understand the PEP5416 board design and figure out how to obtain the 22.05 kHz rate that you
need. The AIC23B chip itself doesn't have any sample rate limitations, it just goes by the external clock signal fed
to it. So you should be able to get what you want by changing an oscillator on the PEP5416 board or otherwise making
a minor mod to the board.

Basic EE 101 -- making hardware mods is often appropriate and can be very effective.

Basic DSP 101 -- don't eat MIPS unless absolutely needed.

-Jeff

> ----- Original Message ----
> From: Jeff Brower
> To: Steve Baker
> Cc: c...
> Sent: Sunday, October 5, 2008 1:27:47 PM
> Subject: Re: [c54x] PLL config problem
> Steve-
>
>> Ok, that's sounds reasonable. I'm going to have to configure
>> a timer to control a recurring interrupt anyway so that
>> the sample rate of the program's filters is met, at least
>> once I get code running in reasonable amounts of time.
>
> Can you explain that further? The sampling rate should be driven by the AIC23, which is in turn driving a McBSP,
> which is in turn driving either interrupts directly or indirectly through DMA. Other clocks in the system might be
> used for monitoring, code profiling / performance measurement, I/O interfaces for processing results, etc -- but would
> not be used for sampling.
>
>> Just a quick word on McBSP + DMA. When you speak of using
>> the two together, do you mean using a ping-pong buffering
>> scheme while using DMA channel sorting?
>
> Typically, DMA fills up two ping-pong buffers, switching back and forth between them. Each time a buffer is filled a
> DMA interrupt is triggered and your code responds. Your code should process the recently filled buffer (ping), while
> DMA is filling the other buffer (pong). A second, separate pair of buffers is used for transmit (D/A).
>
> -Jeff
>
>> ----- Original Message ----
>> From: Jeff Brower
>> To: Steve Baker
>> Cc: c54x@yahoogroups. com
>> Sent: Friday, October 3, 2008 4:28:02 PM
>> Subject: Re: [c54x] PLL config problem
>> Steve-
>>
>> The
>> AIC23 does have discrete settings that include 96, 48, 24, 16, 12, and
>> 8 kHz. I lowered the sample rate to allow more time for processing
>> between reading and writing samples. Even if I entered an invalid
>> frequency, by default, the sampling rate would be set to 48 kHz, and the
>> value of 10 usec would still not make sense. I know that the AIC23_setFreq
>> command is changing the sample rate, because I varied the wait time for
>> other sample rates, and it changed (though didn't make sense for the other
>> sample rates). Perhaps to rectify this situation, I'll directly set
>> the bits in the AIC clock register to achieve the desired sampling rate
>> and then experiment with tones rather than a software spin delay.
>> Thanks for the suggestion.
>> Another suggestion would be to set up Timer1 (not
>> used by DSP/BIOS) and count clock cycles before and after the PEP5416_AIC23_ xx()
>> calls. Then you would know exactly how much time is being used, and
>> how long PEP5416_waitu( ) is actually waiting. One or more of these
>> functions is the 'culprit' and you need a way to find out.
>> -Jeff
>>
>> -----
>> Original Message ----
>> From: Jeff Brower
>> To: Steve Baker
>> Cc: c54x@yahoogroups. com
>> Sent: Thursday, October 2, 2008 6:36:20 PM
>> Subject: Re: [c54x] PLL config problem
>>
>> Hi Steve-
>>
>> I
>> am using DSP/BIOS and had the chip defined before when I wasn't using it.Ok, so DSP/BIOS is in the picture now.
>> That
>> will
>> be good in the long-run.
>>
>> At
>> this point, I don't think the GUI for the PLL config is necessary.
>> I looked at the pin assignments for the clock mode register and set the
>> multiplier that I wanted to use, which should be sufficient. TI support
>> claimed it might be an old unstable GUI that I'm using, though it doesn't
>> really matter anymore.Well TI support likes to run from CCS v3.1. Anything
>> less than v3.3 makes it easier for them to say "please upgrade" instead
>> of dealing with the actual question. If it continues to show in v3.3
>> then they will be helpful.
>>
>> The
>> reason I wanted to try the graphical configuration is because something
>> isn't making sense in my program. When using the lines
>> while(1)
>> {
>>
>> while (!PEP5416_AIC23_ read16(hCodec, &buffer[i])) ;
>>
>> while (!PEP5416_AIC23_ write16(hCodec, buffer[i]));
>>
>> PEP5416_waitu( t)
>> }
>> I varied t until the output started to become distorted
>> to see if this "breaking time" corresponds to the AIC23 sampling rate,
>> which it didn't (it measured 10 usec with an AIC sample rate of 12kHz).
>> I then suspected that I might not be setting my clock speeds properly,
>> which I don't think is the case now, since I used PEP5416_setFreq( Fs ).
>> Perhaps there is more to the PEP5416_waitu( ) function than I realize.You can independently verify the sampling rate
>> by putting
>> some audio tones through your AIC23 loopback -- for example put in a 5.5
>> or 6 kHz tone and listen to what you get out. It should be a) audible
>> if Fs is correct, and b) identical to the input if loopback is working
>> correctly without glitch or buffering issues.
>> All the functions you list will take finite processing
>> time that eats into your sample time. But using up 73 usec doesn't
>> make sense for simple C code functions. Are you sure that Fs can
>> be set continuously on the PEP5416 board and doesn't have discrete settings
>> such as 48 kHz and 96 kHz? If Fs was really 96 kHz then your empirical
>> value for waitu() would make sense.
>> -Jeff
>>
>> -----
>> Original Message ----
>> From: Jeff Brower
>> To: thedoctor152003@ yahoo.com
>> Cc: c54x@yahoogroups. com
>> Sent: Thursday, October 2, 2008 1:19:38 PM
>> Subject: Re: [c54x] PLL config problem
>> Dr-
>>> I'm using CCSv3.1 and the C5416. I attempted
>> to configure the PLL module
>>> using the CSL GUI, and upon compiling, I get the
>> following errors.
>>>
>>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
>> error: identifier "BSCR" is undefined
>>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 187:
>> error: identifier "DIVFCT" is undefined
>>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
>> error: identifier "BSCR" is undefined
>>> "C:/ti/C5400/ csl/include/ csl_pll.h" , line 225:
>> error: identifier "DIVFCT" is undefined
>>>
>>> Anyone experience this before?
>> Did you define CHIP_5416? if you are not using
>> DSP/BIOS (which I recall that you're
>> not), then you have to manually define the chip type
>> for CSL purposes. You can do
>> this under Project | Build Options | Preprocessor
>> | Define Symbols.
>> Also, did you see this page:
>> http://c5000.
>> spectrumdigital. com/pep5416/ docs/bsp/ bsl.html
>> which would apply to the PEP5416 board that you are
>> using.
>> -Jeff