|
Hi there, I hope someone can offer me a
suggestion!
I'm using a 'C5402 for wireless audio
transmission, which is performing data compression and forward error
correction. The receiver side performs error detection and
decompression. My problem is as follows:
The bit-rate from the ADC to the input of the transmitter
DSP is 512Kbps. After the compression, and error
coding, the output data rate is exactly 253/832 times the input data rate, and
I need to produce a bit clock to shift the data out of the serial
port. This is obviously a very awkward clock frequency to generate!
The input and output must be completely synchronised (derived from the same
16.834MHz master clock), any repetition or deletion of data will confuse the
receiver no end. Also, I can't add too many extra redundant words to
the output data stream (to simplify the divisor) because I'll loose
bandwidth. The error coding algorithm is not flexible. The
programmable clock register in the C5402 is just not up to the job! So
what do I do? If I have to use an external device (microcontroller etc.)
for clock generation, what should I use? FPGA? Seems like overkill
to me.
I would be very grateful to those who can offer
ideas/comments. It seems like a straightforward problem, but the solution
eludes me.
Many thanks
Tim
|
Input/output data synchronisation (hardware)
Started by ●July 6, 2001
