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Hello, I was wondering if you can help me, I have a c5402 DSK and I am trying to run the audio program supplied with the board (c:\ti\c5400\examples\bios\audio ). I have successfully re-written the DSS_init function to setup and enable the AD50 codec and McBSP port. The program runs but the Hardware ISR for the McBSP never seems to be called. I have noticed that the audio.cdb file sets the IPTR at 0xFF80 and the MP/!MC bit = 1, I have not changed the CPLD registers from the default settings, so this should place the vector table in FLASH. After reading SPRA618.pdf I am presuming that CCS File -> Load Program uses the bootloader in HPI mode, to load the audio.out into memory and as my DIP switches are in there default positions (i.e. MP/!MC = 0) this would place address 0xFF80 in on-chip ROM. This would confirm why my ISR is not working (ROM cannot be written to), but all that I have written in this paragraph is only what I am presumming, as I cannot find any documentation on what CCS File -> Load Program actually does. To get to the point, I would be most grateful if you could confirm my presumtions or tell me what is actually happening. If any of this is documentied anywhere, please point me in the right direction. Also I am curious to know what would happen if DIP switch 2 was turned off (MP/!MC = 1) would CCS still be able load programs with the ROM disabled (hence no bootloader). And what difference does it make if NMIEN bit in CPLD reg CNTL1 is left at default (0 = NMI disable) ?- does CCS use this for debugging or anything Thanks for your help. Chris Durkin. |
CCS File -> Load Progam
Started by ●April 11, 2002
