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Hello all, I am facing problems with the configuration of McBSP and Audio Codec .The required file is attached for your reference. I hope you will be able to point out where the mistake lies. I have the following issues regarding McBSP 1) Regarding frame width configuration:] Here I am configuring McBSP0 of 5402 in master mode, BCLKX0 =2.048 MHz (system clock/ 16 (system clock = 32.768Mhz)) BFSX0 = 8 KHz (BCLKX0/256) Frame Width = one CLKG period which is 0.488us in this case. these configurations are done when McBSP is in reset (XRST=RRST=FRST=GSRT=0) and I am removing Sample Rate Generator ,Transmitter and Receiver from reset ,one after another. I am getting proper wave forms when Sample Rate Generator is removed from reset, frame width will increase to 0.488us to 16us when Transmitter is enabled . I am attaching my asm file for your reference. 2) I am not able to communicate with Audio Codec (TLV320AIC22) . Here, I am configuring McBSP in Master mode .MCLK of Audio Codec is derived from Clock out of DSP.For Audio Codec MCLK is not available at reset time because at reset time DSP will also be in Reset condition. Is this a problem?I am attaching schematic page of DSP and Audio Codec for your reference. Can I get a sample Audio Codec initialization file(for TLV320AIC22) ? Has anybody worked on this? If more inputs are needed, please mail me back. I am desperately looking forward for a solution.... Regards, Girish | |||
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.mmregs .algebraic .data SPSA0 .set 0038h ;Sub-bank Address Register SPSD0 .set 0039h ;Sub-bank data Register SPCR10 .set 0000h ; McBSP Ser Port Ctrl Reg1 SPCR20 .set 0001h ; McBSP Ser Port Ctrl Reg2 RCR10 .set 0002h ; McBSP Rx Ctrl Reg1 RCR20 .set 0003h ; McBSP Rx Ctrl Reg2 XCR10 .set 0004h ; McBSP Tx Ctrl Reg1 XCR20 .set 0005h ; McBSP Tx Ctrl Reg2 SRGR10 .set 0006h ; McBSP Sample Rate Gen Reg1 SRGR20 .set 0007h ; McBSP Sample Rate Gen Reg2 MCR10 .set 0008h ; McBSP Multichan Reg1 MCR20 .set 0009h ; McBSP Multichan Reg2 RCERA0 .set 000Ah ; McBSP Rx Chan Enable Reg Partition A RCERB0 .set 000Bh ; McBSP Rx Chan Enable Reg Partition B XCERA0 .set 000Ch ; McBSP Tx Chan Enable Reg Partition A XCERB0 .set 000Dh ; McBSP Tx Chan Enable Reg Partition B PCR0 .set 000Eh ; McBSP Pin Ctrl Reg .text ;*******************************************************************************\ ******** ;%%%%%%%%%%%%%%%%%%%%%%%% mcbsp intialization %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% ;*******************************************************************************\ ******** mmr(SPSA0) = #SPCR10 mmr(SPSD0) = #1000h ; repeat(#6) ; nop mmr(SPSA0) = #SPCR20;; transmeter is in reset mode and grst = 0 frst = 1 mmr(SPSD0) = #0220h repeat(#6) nop mmr(SPSA0) = #PCR0 mmr(SPSD0) = #00a03h ;; configured in master mode repeat(#6) nop mmr(SPSA0) = #RCR10 mmr(SPSD0) = #0140h ;; configured for one 16bit words per frame repeat(#6) nop mmr(SPSA0) = #RCR20 mmr(SPSD0) = #0004h ;; single phase no companding repeat(#6) nop mmr(SPSA0) = #XCR10 mmr(SPSD0) = #0140h ;; configured for two 16bit words per frame repeat(#6) nop mmr(SPSA0) = #XCR20 mmr(SPSD0) = #0004h ;; for single phase , no companding data transfer starts with msb first repeat(#6) nop ;; zero bit data dealy mmr(SPSA0) = #SRGR10 mmr(SPSD0) = #0000fh ;;devide by 16 repeat(#6) nop mmr(SPSA0) = #SRGR20 mmr(SPSD0) = #30ffh ;;frame sync period = 256 clock pulses repeat(#6) nop nop mmr(SPSA0) = #MCR10 ; mmr(SPSD0) = #01h ;; ; repeat(#6) ; NOP ; mmr(SPSA0) = #MCR20 ; mmr(SPSD0) = #0003h ;; ; nop ; mmr(SPSA0) = #RCERA0 ; mmr(SPSD0) = #0003h ;; enabling 0-3 channels ; nop ; mmr(SPSA0) = #RCERB0 ; mmr(SPSD0) = #0000h ;; disabling all channles in b block ; nop ; mmr(SPSA0) = #XCERA0 ; mmr(SPSD0) = #0003h ;; enabling 0-3 channels ; nop ; mmr(SPSA0) = #XCERB0 ; mmr(SPSD0) = #0000h ; nop ; nop ;;******************************************************************************\ *********** ;*;*********************removing mcbsp from reset****************************************** ;**;****************************************************************************\ ********** mmr(SPSA0) = #SPCR20 mmr(SPSD0) = #02c0h ;; remove sample rate generator from reset repeat(#6h) nop mmr(SPSA0) = #SPCR20 mmr(SPSD0) = #02c1h ;; remove transmitter from reset nop nop nop nop nop nop nop nop mmr(SPSA0) = #SPCR10 ;; remove reciver from reset mmr(SPSD0) = #1001h nop nop nop nop nop nop nop nop ;**********************mcbsp intialized in master mode************************************** .end ; |
problems on McBSP and audio codec interfacing
Started by ●May 24, 2002
