TMS5509A und External Flash on EMIF

Hello,
i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running
on EMIF.

My Configuration is:

EMIF_FSET(EGCR,MEMFREQ,4); //MEMFREQ 1/16 CPU
EMIF_FSET(EGCR,MEMCEN,1); //MEMClock on CLKMEM
EMIF_FSET(EGCR,NOHOLD,0); //MEMClock on CLKMEM

EMIF_FSET(CE21,MTYPE,1); //16 bit async
EMIF_FSET(CE21,RDSETUP,1); //RD Setup Clock Time
EMIF_FSET(CE21,RDSTROBE,17); //RD Setup Clock Time
EMIF_FSET(CE21,RDHOLD,3); //RD Setup Clock Time

EMIF_FSET(CE22,WRSETUP,1); //RD Setup Clock Time
EMIF_FSET(CE22,WRSTROBE,17); //RD Setup Clock Time
EMIF_FSET(CE22,WRHOLD,3);

To write to Flash i do that in a loop:

*(Uint16*) 0x80FF00=0xFF00;

but cant neither see the CE2 signal going down nor
the 0xFF00 on the adress bus and the data bus.
Unfortunately i cannot find any useful documentation
about my problem.

I would be very glad if anybody could help me.

Thanks,
Christoph Start a New Thread

Christoph-

> i have spent several hours trying to get my Flash Memory (AT49LV1024, 1Mbit) running
> on EMIF.
>
> My Configuration is:
>
> EMIF_FSET(EGCR,MEMFREQ,4); //MEMFREQ 1/16 CPU
> EMIF_FSET(EGCR,MEMCEN,1); //MEMClock on CLKMEM
> EMIF_FSET(EGCR,NOHOLD,0); //MEMClock on CLKMEM
>
> EMIF_FSET(CE21,MTYPE,1); //16 bit async
> EMIF_FSET(CE21,RDSETUP,1); //RD Setup Clock Time
> EMIF_FSET(CE21,RDSTROBE,17); //RD Setup Clock Time
> EMIF_FSET(CE21,RDHOLD,3); //RD Setup Clock Time
>
> EMIF_FSET(CE22,WRSETUP,1); //RD Setup Clock Time
> EMIF_FSET(CE22,WRSTROBE,17); //RD Setup Clock Time
> EMIF_FSET(CE22,WRHOLD,3);
>
> To write to Flash i do that in a loop:
>
> *(Uint16*) 0x80FF00=0xFF00;
>
> but cant neither see the CE2 signal going down nor
> the 0xFF00 on the adress bus and the data bus.
> Unfortunately i cannot find any useful documentation
> about my problem.
>
> I would be very glad if anybody could help me.

Aren't you supposed to have Flash on CE1? This is the recommended TI solution -- for
sure it has to be there if you expect to boot from Flash. I wouldn't try it any
other way, given the strangenesses in connecting SRAM and SDRAM to CE2.

-Jeff Start a New Thread