problems with McBSP as master with Atmel AT45DB642D as slave

I am trying to set up the McBSP0 as a master connected to an Atmel AT45DB642D data flash chip and I cannot get things to work.
In hooking up a logic analyzer I can see that I am getting a CLK and the data is transmitting on the DX line but I never read back anything.
I get back nothing even when I do a simple command like reading the status register. I was wondering if anything is wrong with my McBSP configuration that can be seen offhand. Here it is:

static MCBSP_Config ConfigStopClock = {
MCBSP_SPCR1_RMK(
MCBSP_SPCR1_DLB_OFF,
MCBSP_SPCR1_RJUST_RZF,
MCBSP_SPCR1_CLKSTP_NODELAY,
MCBSP_SPCR1_DXENA_OFF,
MCBSP_SPCR1_ABIS_DISABLE,
MCBSP_SPCR1_RINTM_RRDY,
MCBSP_SPCR1_RSYNCERR_NO,
MCBSP_SPCR1_RRST_DISABLE
),
MCBSP_SPCR2_RMK(
MCBSP_SPCR2_FREE_YES,
MCBSP_SPCR2_SOFT_NO,
MCBSP_SPCR2_FRST_RESET,
MCBSP_SPCR2_GRST_RESET,
MCBSP_SPCR2_XINTM_XRDY,
MCBSP_SPCR2_XSYNCERR_NO,
MCBSP_SPCR2_XRST_DISABLE
),
MCBSP_RCR1_RMK(
MCBSP_RCR1_RFRLEN1_OF(0),
MCBSP_RCR1_RWDLEN1_8BIT
),
MCBSP_RCR2_RMK(
MCBSP_RCR2_RPHASE_SINGLE,
MCBSP_RCR2_RFRLEN2_OF(0),
MCBSP_RCR2_RWDLEN2_8BIT,
MCBSP_RCR2_RCOMPAND_MSB,
MCBSP_RCR2_RFIG_NO,
MCBSP_RCR2_RDATDLY_1BIT
),
MCBSP_XCR1_RMK(
MCBSP_XCR1_XFRLEN1_OF(0),
MCBSP_XCR1_XWDLEN1_8BIT
),
MCBSP_XCR2_RMK(
MCBSP_XCR2_XPHASE_SINGLE,
MCBSP_XCR2_XFRLEN2_OF(0),
MCBSP_XCR2_XWDLEN2_8BIT,
MCBSP_XCR2_XCOMPAND_MSB,
MCBSP_XCR2_XFIG_NO,
MCBSP_XCR2_XDATDLY_1BIT
),
MCBSP_SRGR1_RMK(
MCBSP_SRGR1_FWID_OF(0),
MCBSP_SRGR1_CLKGDV_OF(1)
),
MCBSP_SRGR2_RMK(
MCBSP_SRGR2_GSYNC_FREE,
MCBSP_SRGR2_CLKSP_RISING,
MCBSP_SRGR2_CLKSM_INTERNAL,
MCBSP_SRGR2_FSGM_DXR2XSR,
MCBSP_SRGR2_FPER_OF(0)
),
MCBSP_MCR1_RMK(
MCBSP_MCR1_RMCME_NO,
MCBSP_MCR1_RPBBLK_SF1,
MCBSP_MCR1_RPABLK_SF0,
MCBSP_MCR1_RCBLK_SF0,
MCBSP_MCR1_RMCM_CHENABLE
),
MCBSP_MCR2_RMK(
MCBSP_MCR2_XMCME_NO,
MCBSP_MCR2_XPBBLK_SF1,
MCBSP_MCR2_XPABLK_SF0,
MCBSP_MCR2_XCBLK_SF0,
MCBSP_MCR2_XMCM_ENNOMASK
),
MCBSP_PCR_RMK(
MCBSP_PCR_IDLEEN_RESET,
MCBSP_PCR_XIOEN_SP,
MCBSP_PCR_RIOEN_SP,
MCBSP_PCR_FSXM_INTERNAL,
MCBSP_PCR_FSRM_EXTERNAL,
MCBSP_PCR_CLKXM_OUTPUT,
MCBSP_PCR_CLKRM_INPUT,
MCBSP_PCR_SCLKME_NO,
MCBSP_PCR_DXSTAT_0,
MCBSP_PCR_FSXP_ACTIVELOW,
MCBSP_PCR_FSRP_ACTIVEHIGH,
MCBSP_PCR_CLKXP_RISING,
MCBSP_PCR_CLKRP_FALLING
),
MCBSP_RCERA_DEFAULT,
MCBSP_RCERB_DEFAULT,
MCBSP_RCERC_DEFAULT,
MCBSP_RCERD_DEFAULT,
MCBSP_RCERE_DEFAULT,
MCBSP_RCERF_DEFAULT,
MCBSP_RCERG_DEFAULT,
MCBSP_RCERH_DEFAULT,
MCBSP_XCERA_DEFAULT,
MCBSP_XCERB_DEFAULT,
MCBSP_XCERC_DEFAULT,
MCBSP_XCERD_DEFAULT,
MCBSP_XCERE_DEFAULT,
MCBSP_XCERF_DEFAULT,
MCBSP_XCERG_DEFAULT,
MCBSP_XCERH_DEFAULT
};

I appreciate any help.

thanks
Monika Start a New Thread

Monika-

> I am trying to set up the McBSP0 as a master connected to an Atmel AT45DB642D data flash chip and I cannot get things
> to work.
> In hooking up a logic analyzer I can see that I am getting a CLK and the data is transmitting on the DX line but I
> never read back anything.
> I get back nothing even when I do a simple command like reading the status register. I was wondering if anything is
> wrong with my McBSP configuration that can be seen offhand. Here it is:

One thing I notice in your setup code is that you have Tx clock internal (master) but Rx clock as external. That
would mean you tied Rx clock and Tx clock lines for the McBSP port you're using together outside the DSP? If not,
then Rx needs to be internal also.

That may not be the whole problem. In general, if you have a logic analyzer set up and you're to the point of
verifying clock and data output from the DSP, then I would continue that way. If the first command you're trying to
send is a simple "read status register", have you verified the entire command sequence -- clock, clock polarity
relative to data bits changing, data bit order, etc -- is correct according to the AT45DB624D data sheet? And if so,
what comes back from the Atmel chip?

Before worrying that software gets incorrect McBSP DRR results, you would want to verify the Atmel chip is sending
exactly what is expected according to its data sheet. It's especially important to verify clock edge polarity
relative to data bit sampling, as it could appear to work in software even if clock polarity is opposite, then later
(under more stressful conditions) it would fail.

-Jeff

> static MCBSP_Config ConfigStopClock = {
> MCBSP_SPCR1_RMK(
> MCBSP_SPCR1_DLB_OFF,
> MCBSP_SPCR1_RJUST_RZF,
> MCBSP_SPCR1_CLKSTP_NODELAY,
> MCBSP_SPCR1_DXENA_OFF,
> MCBSP_SPCR1_ABIS_DISABLE,
> MCBSP_SPCR1_RINTM_RRDY,
> MCBSP_SPCR1_RSYNCERR_NO,
> MCBSP_SPCR1_RRST_DISABLE
> ),
> MCBSP_SPCR2_RMK(
> MCBSP_SPCR2_FREE_YES,
> MCBSP_SPCR2_SOFT_NO,
> MCBSP_SPCR2_FRST_RESET,
> MCBSP_SPCR2_GRST_RESET,
> MCBSP_SPCR2_XINTM_XRDY,
> MCBSP_SPCR2_XSYNCERR_NO,
> MCBSP_SPCR2_XRST_DISABLE
> ),
> MCBSP_RCR1_RMK(
> MCBSP_RCR1_RFRLEN1_OF(0),
> MCBSP_RCR1_RWDLEN1_8BIT
> ),
> MCBSP_RCR2_RMK(
> MCBSP_RCR2_RPHASE_SINGLE,
> MCBSP_RCR2_RFRLEN2_OF(0),
> MCBSP_RCR2_RWDLEN2_8BIT,
> MCBSP_RCR2_RCOMPAND_MSB,
> MCBSP_RCR2_RFIG_NO,
> MCBSP_RCR2_RDATDLY_1BIT
> ),
> MCBSP_XCR1_RMK(
> MCBSP_XCR1_XFRLEN1_OF(0),
> MCBSP_XCR1_XWDLEN1_8BIT
> ),
> MCBSP_XCR2_RMK(
> MCBSP_XCR2_XPHASE_SINGLE,
> MCBSP_XCR2_XFRLEN2_OF(0),
> MCBSP_XCR2_XWDLEN2_8BIT,
> MCBSP_XCR2_XCOMPAND_MSB,
> MCBSP_XCR2_XFIG_NO,
> MCBSP_XCR2_XDATDLY_1BIT
> ),
> MCBSP_SRGR1_RMK(
> MCBSP_SRGR1_FWID_OF(0),
> MCBSP_SRGR1_CLKGDV_OF(1)
> ),
> MCBSP_SRGR2_RMK(
> MCBSP_SRGR2_GSYNC_FREE,
> MCBSP_SRGR2_CLKSP_RISING,
> MCBSP_SRGR2_CLKSM_INTERNAL,
> MCBSP_SRGR2_FSGM_DXR2XSR,
> MCBSP_SRGR2_FPER_OF(0)
> ),
> MCBSP_MCR1_RMK(
> MCBSP_MCR1_RMCME_NO,
> MCBSP_MCR1_RPBBLK_SF1,
> MCBSP_MCR1_RPABLK_SF0,
> MCBSP_MCR1_RCBLK_SF0,
> MCBSP_MCR1_RMCM_CHENABLE
> ),
> MCBSP_MCR2_RMK(
> MCBSP_MCR2_XMCME_NO,
> MCBSP_MCR2_XPBBLK_SF1,
> MCBSP_MCR2_XPABLK_SF0,
> MCBSP_MCR2_XCBLK_SF0,
> MCBSP_MCR2_XMCM_ENNOMASK
> ),
> MCBSP_PCR_RMK(
> MCBSP_PCR_IDLEEN_RESET,
> MCBSP_PCR_XIOEN_SP,
> MCBSP_PCR_RIOEN_SP,
> MCBSP_PCR_FSXM_INTERNAL,
> MCBSP_PCR_FSRM_EXTERNAL,
> MCBSP_PCR_CLKXM_OUTPUT,
> MCBSP_PCR_CLKRM_INPUT,
> MCBSP_PCR_SCLKME_NO,
> MCBSP_PCR_DXSTAT_0,
> MCBSP_PCR_FSXP_ACTIVELOW,
> MCBSP_PCR_FSRP_ACTIVEHIGH,
> MCBSP_PCR_CLKXP_RISING,
> MCBSP_PCR_CLKRP_FALLING
> ),
> MCBSP_RCERA_DEFAULT,
> MCBSP_RCERB_DEFAULT,
> MCBSP_RCERC_DEFAULT,
> MCBSP_RCERD_DEFAULT,
> MCBSP_RCERE_DEFAULT,
> MCBSP_RCERF_DEFAULT,
> MCBSP_RCERG_DEFAULT,
> MCBSP_RCERH_DEFAULT,
> MCBSP_XCERA_DEFAULT,
> MCBSP_XCERB_DEFAULT,
> MCBSP_XCERC_DEFAULT,
> MCBSP_XCERD_DEFAULT,
> MCBSP_XCERE_DEFAULT,
> MCBSP_XCERF_DEFAULT,
> MCBSP_XCERG_DEFAULT,
> MCBSP_XCERH_DEFAULT
> };
>
> I appreciate any help.
>
> thanks
> Monika Start a New Thread