How to configure receive interrupt to work nice in 5509a. If I configure MCBSP
to produce interrupt when RRDY bit changes from 0 to 1 (SPCR1 bits 5-4 00b)
interrupts keep coming all the time, even when there is nothing to receive. Any
other bit combination doesn't generate an interrupt at all.
When I use receiver polling mode it works ok.
Polling mode loop:
while (!MCBSP_rrdy(hMcbsp2));
MCBSP2 is in use, so HWI18 is the interrupt.
Is there any good documentation about interrupts. I think TI's
documentation is horrible.
MCBSP configuration:
/* Config Structures */
MCBSP_Config mcbspCfg2 = {
0x1800, /* Serial Port Control Register 1 */
0x0000, /* Serial Port Control Register 2 */
0x0040, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0000, /* Transmit Control Register 2 */
0x0001, /* Sample Rate Generator Register 1 */
0x6000, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x300e, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Receive Channel Enable Register Partition C */
0x0000, /* Receive Channel Enable Register Partition D */
0x0000, /* Receive Channel Enable Register Partition E */
0x0000, /* Receive Channel Enable Register Partition F */
0x0000, /* Receive Channel Enable Register Partition G */
0x0000, /* Receive Channel Enable Register Partition H */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000, /* Transmit Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition C */
0x0000, /* Transmit Channel Enable Register Partition D */
0x0000, /* Transmit Channel Enable Register Partition E */
0x0000, /* Transmit Channel Enable Register Partition F */
0x0000, /* Transmit Channel Enable Register Partition G */
0x0000 /* Transmit Channel Enable Register Partition H */
};
5509a MCBSP SPI slave and receive interrupts
Started by ●November 1, 2007
Reply by ●November 2, 20072007-11-02
Reply by ●January 24, 20082008-01-24
How to configure receive interrupt to work nice in 5509a. If I configure MCBSP
to produce interrupt when RRDY bit changes from 0 to 1 (SPCR1 bits 5-4 00b)
interrupts keep coming all the time, even when there is nothing to receive. Any
other bit combination doesn't generate an interrupt at all.
>
>When I use receiver polling mode it works ok.
>Polling mode loop:
> while (!MCBSP_rrdy(hMcbsp2));
>
>MCBSP2 is in use, so HWI18 is the interrupt.
>
>Is there any good documentation about interrupts. I think TI's documentation is horrible.
>
I'll try to explain a bit more, if someone could help me out.
I'm using DSP as SPI slave device. SPI-master sends different messages to slave and those messages are 16-bit long frames. First frame always tells how long message is coming. So there is an interrupt on every character that comes. It's fine.
When there is nothing to send from master, it has to ask from slave (DSP) does it have something to send. If there is something to send, slave had already put a character in RX register. Problem is when there is nothing to send or nothing to receive, interrupts come every time master checks the slave (does slave have something to send). It takes resources for nothing.
Bigger problem is priority of McBSP2 interrupt and the size of the RX buffer. If the DSP is doing something with a higher prioirity is misses characters from the coming messages. Master keeps characters coming even slave doesn't have time to handle them.
Is there any good examples of a powerful SPI-master-slave -code?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
>
>When I use receiver polling mode it works ok.
>Polling mode loop:
> while (!MCBSP_rrdy(hMcbsp2));
>
>MCBSP2 is in use, so HWI18 is the interrupt.
>
>Is there any good documentation about interrupts. I think TI's documentation is horrible.
>
I'll try to explain a bit more, if someone could help me out.
I'm using DSP as SPI slave device. SPI-master sends different messages to slave and those messages are 16-bit long frames. First frame always tells how long message is coming. So there is an interrupt on every character that comes. It's fine.
When there is nothing to send from master, it has to ask from slave (DSP) does it have something to send. If there is something to send, slave had already put a character in RX register. Problem is when there is nothing to send or nothing to receive, interrupts come every time master checks the slave (does slave have something to send). It takes resources for nothing.
Bigger problem is priority of McBSP2 interrupt and the size of the RX buffer. If the DSP is doing something with a higher prioirity is misses characters from the coming messages. Master keeps characters coming even slave doesn't have time to handle them.
Is there any good examples of a powerful SPI-master-slave -code?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●January 25, 20082008-01-25
Why don't you use DMA to transfert all your incoming data from your SPI
to you internal DSP mem?
-Remove your SPI interrupt.
-allocate a sufficient memory space in your DSP mem
-Set the DMA to transfert a 16-bit word on each SPI event into this
memory.
-and when you're not busy processing other threads, just process what
was copy to this mem section.
Does this look feasible for your application?
regards.
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
to you internal DSP mem?
-Remove your SPI interrupt.
-allocate a sufficient memory space in your DSP mem
-Set the DMA to transfert a 16-bit word on each SPI event into this
memory.
-and when you're not busy processing other threads, just process what
was copy to this mem section.
Does this look feasible for your application?
regards.
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●January 26, 20082008-01-26
Actually DMA transfer came into my mind just before You sent your suggestion
about using it.
First thing I have to do is to check is there any DMA channels free anymore.
Is it possible do the messaging through DMA because it has to have some kind of intelligence? The length of the message varies and first 16 bit tells the length. I can always reserve enough space for longest message but how I can be sure there won't be two messages?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
First thing I have to do is to check is there any DMA channels free anymore.
Is it possible do the messaging through DMA because it has to have some kind of intelligence? The length of the message varies and first 16 bit tells the length. I can always reserve enough space for longest message but how I can be sure there won't be two messages?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●January 28, 20082008-01-28
I've set my DMA up to tell me when my buffer is full. When that happens,
I
get an interrupt in which I post a semaphore to take care of the buffer and
to switch the DMA to another buffer.
You should be able to set your DMA interrupt up in a similar manner. You
need to know when those first 16 bits have been received and get some sort
of interrupt for that event. Your DMA interrupt routine could then read the
16 bits to decide what to do next, if it is to go back to sleep or to
continue receiving information.
/S
On 1/25/08, a...@gmail.com wrote:
>
> Actually DMA transfer came into my mind just before You sent your
> suggestion about using it.
>
> First thing I have to do is to check is there any DMA channels free
> anymore.
>
> Is it possible do the messaging through DMA because it has to have some
> kind of intelligence? The length of the message varies and first 16 bit
> tells the length. I can always reserve enough space for longest message but
> how I can be sure there won't be two messages?
>
get an interrupt in which I post a semaphore to take care of the buffer and
to switch the DMA to another buffer.
You should be able to set your DMA interrupt up in a similar manner. You
need to know when those first 16 bits have been received and get some sort
of interrupt for that event. Your DMA interrupt routine could then read the
16 bits to decide what to do next, if it is to go back to sleep or to
continue receiving information.
/S
On 1/25/08, a...@gmail.com wrote:
>
> Actually DMA transfer came into my mind just before You sent your
> suggestion about using it.
>
> First thing I have to do is to check is there any DMA channels free
> anymore.
>
> Is it possible do the messaging through DMA because it has to have some
> kind of intelligence? The length of the message varies and first 16 bit
> tells the length. I can always reserve enough space for longest message but
> how I can be sure there won't be two messages?
>
Reply by ●February 7, 20082008-02-07
Thank you all for ideas you've given me this far.
My next plan is to get one character which tells the length of the coming message at the beginning. I should reconfigure mcbsp and DMA controller in intterrupt routine that incoming character gives.
After that rest of the characters comes in one frame and are read by DMA to memory. DMA then gives an interrupt where I disable DMA and start all over again.
Couple of questions:
1. How do I configure SPI (mcbsp) bus to read multiple 16-bit words in one frame? All examples I've seen send and receive only one character (bit length varies) in one frame.
2. How do I configure DMA to read multiple characters from SPI bus to memory and to give an interrupt after transfer is done?
3. How big is the buffer which handles incoming characters (maximum character count in one frame)?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
My next plan is to get one character which tells the length of the coming message at the beginning. I should reconfigure mcbsp and DMA controller in intterrupt routine that incoming character gives.
After that rest of the characters comes in one frame and are read by DMA to memory. DMA then gives an interrupt where I disable DMA and start all over again.
Couple of questions:
1. How do I configure SPI (mcbsp) bus to read multiple 16-bit words in one frame? All examples I've seen send and receive only one character (bit length varies) in one frame.
2. How do I configure DMA to read multiple characters from SPI bus to memory and to give an interrupt after transfer is done?
3. How big is the buffer which handles incoming characters (maximum character count in one frame)?
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
Reply by ●February 7, 20082008-02-07
It seems impossible to me to receive multiple words in one frame in
clock stop mode, if you refer one frame as continuous low of CSn. You
can configure DMA that receives multiple words in one frame by
following the datasheet. The number of words in frame is decided by
the size of buffer you assign to DMA, the only limit is your memory
size or the size of the counter in DMA whatever is smaller.
Wei
--- In c..., aimoparru@... wrote:
> Thank you all for ideas you've given me this far.
>
> My next plan is to get one character which tells the length of the
coming message at the beginning. I should reconfigure mcbsp and
DMA controller in intterrupt routine that incoming character gives.
>
> After that rest of the characters comes in one frame and are read by
DMA to memory. DMA then gives an interrupt where I disable DMA and
start all over again.
>
> Couple of questions:
> 1. How do I configure SPI (mcbsp) bus to read multiple 16-bit words in
one frame? All examples I've seen send and receive only one character
(bit length varies) in one frame.
> 2. How do I configure DMA to read multiple characters from SPI bus
to memory and to give an interrupt after transfer is done?
> 3. How big is the buffer which handles incoming characters
(maximum character count in one frame)?
>
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
clock stop mode, if you refer one frame as continuous low of CSn. You
can configure DMA that receives multiple words in one frame by
following the datasheet. The number of words in frame is decided by
the size of buffer you assign to DMA, the only limit is your memory
size or the size of the counter in DMA whatever is smaller.
Wei
--- In c..., aimoparru@... wrote:
> Thank you all for ideas you've given me this far.
>
> My next plan is to get one character which tells the length of the
coming message at the beginning. I should reconfigure mcbsp and
DMA controller in intterrupt routine that incoming character gives.
>
> After that rest of the characters comes in one frame and are read by
DMA to memory. DMA then gives an interrupt where I disable DMA and
start all over again.
>
> Couple of questions:
> 1. How do I configure SPI (mcbsp) bus to read multiple 16-bit words in
one frame? All examples I've seen send and receive only one character
(bit length varies) in one frame.
> 2. How do I configure DMA to read multiple characters from SPI bus
to memory and to give an interrupt after transfer is done?
> 3. How big is the buffer which handles incoming characters
(maximum character count in one frame)?
>
Check Out Industry's First Single-Chip, Multi-Format, Real-Time HD Video Transcoding Solution for Commercial & Consumer End Equipment: www.ti.com/dm6467
