Hi All,
I've got a serial communications bus (400Kb/s) between two DSPs (C54 to
C55) that has errors when its received in the buffer (McBSP via DMA).
The errors are normally a 1 bit shift in the end 8bits of 1 16bit word
only*, between the middle and end of the message where the entire
message is 30 words long (60B). I presume what is happening is something
is on the edge and is being interpreted incorrectly but the framesync is
preventing any word after that in the message becoming corrupt.
* Example Error
Word 27 of 30 taken from Logic Analyser : 01010101 10010010
Word 27 of 30 taken from Software (Error) : 01010101 10001001
The PCB layout is a fairly simply 12cm track with 4 micro-vias, cross
talk is insignificant but rise and fall timings do not meet datasheet
specification. In the C55 datasheet rise and fall timings are specified
to be 5ns where these are measuring 26ns probably due to the 470R series
resistors on each line, on one side of a connector. I would normally
short the resistors out to check the differences on the scope but this
is currently not possible until next week so was wondering if anyone had
any insight as to if the timings would cause this sort of problem?
Many Thanks,
Bob
C54 to C55 McBSP Clock, Data, Framesync
Started by ●September 21, 2008
Reply by ●September 22, 20082008-09-22
Bob-
> I've got a serial communications bus (400Kb/s) between two DSPs (C54 to
> C55) that has errors when its received in the buffer (McBSP via DMA).
> The errors are normally a 1 bit shift in the end 8bits of 1 16bit word
> only*, between the middle and end of the message where the entire
> message is 30 words long (60B). I presume what is happening is something
> is on the edge and is being interpreted incorrectly but the framesync is
> preventing any word after that in the message becoming corrupt.
>
> * Example Error
> Word 27 of 30 taken from Logic Analyser : 01010101 10010010
> Word 27 of 30 taken from Software (Error) : 01010101 10001001
>
> The PCB layout is a fairly simply 12cm track with 4 micro-vias, cross
> talk is insignificant but rise and fall timings do not meet datasheet
> specification. In the C55 datasheet rise and fall timings are specified
> to be 5ns where these are measuring 26ns probably due to the 470R series
> resistors on each line, on one side of a connector. I would normally
> short the resistors out to check the differences on the scope but this
> is currently not possible until next week so was wondering if anyone had
> any insight as to if the timings would cause this sort of problem?
1) Why 470 ohm series Rs? That's a relatively high value that will reduce rise/fall times... I would expect something
in the range of 25 to 100 is enough to prevent ringing.
2) Have you checked to make sure bit sampling is on the correct clock edge? For example Tx bits are changing on
rising edge and Rx bits are being sampled on falling edge? If this is not happening it should be obvious on the
scope.
3) What does this mean "...but the framesync is preventing any word after that in the message becoming corrupt". Do
you mean you typically get one error, in one word, then all other words after that are Ok?
-Jeff
> I've got a serial communications bus (400Kb/s) between two DSPs (C54 to
> C55) that has errors when its received in the buffer (McBSP via DMA).
> The errors are normally a 1 bit shift in the end 8bits of 1 16bit word
> only*, between the middle and end of the message where the entire
> message is 30 words long (60B). I presume what is happening is something
> is on the edge and is being interpreted incorrectly but the framesync is
> preventing any word after that in the message becoming corrupt.
>
> * Example Error
> Word 27 of 30 taken from Logic Analyser : 01010101 10010010
> Word 27 of 30 taken from Software (Error) : 01010101 10001001
>
> The PCB layout is a fairly simply 12cm track with 4 micro-vias, cross
> talk is insignificant but rise and fall timings do not meet datasheet
> specification. In the C55 datasheet rise and fall timings are specified
> to be 5ns where these are measuring 26ns probably due to the 470R series
> resistors on each line, on one side of a connector. I would normally
> short the resistors out to check the differences on the scope but this
> is currently not possible until next week so was wondering if anyone had
> any insight as to if the timings would cause this sort of problem?
1) Why 470 ohm series Rs? That's a relatively high value that will reduce rise/fall times... I would expect something
in the range of 25 to 100 is enough to prevent ringing.
2) Have you checked to make sure bit sampling is on the correct clock edge? For example Tx bits are changing on
rising edge and Rx bits are being sampled on falling edge? If this is not happening it should be obvious on the
scope.
3) What does this mean "...but the framesync is preventing any word after that in the message becoming corrupt". Do
you mean you typically get one error, in one word, then all other words after that are Ok?
-Jeff
