Re: 5502 problems w/PCB redesign: max CPU 132MHz, EMIF 33MHz, peripherals 66MHz

John-

> We've been developing code on a custom PCB for the 5502 chip. We
> realized we needed a port expander, so we made a revision to our
> custom board. However, now we are not able to configure the PLL to get
> a CPU clock speed above 132 MHz AND have functional SDRAM interface or
> peripherals. The emulation freezes when the EMIF is utilized if
> PLL_DIV3 is not set to 0x8003, regardless of clock speed, or if the
> resulting EMIF clock would be greater than 33 MHz, confining us to the
> CPU speed above. Furthermore, the fast and slow peripherals are
> problematic beyond 66 MHz (PLL_DIV1, PLL_DIV2 set to 0x8001).

In general it's not a good idea to add peripherals to a 55x EMIF when an SDRAM
interface is being used. That makes the design considerably more complex, and
requires careful attention to impedance matching. Did you do high speed signal
simulation of the layout prior to PCB fab? If not then do you have some series Rs
you can play with and measure waveform shapes on a dig scope? You would need a good
scope, 1 GHz at least.

What devices are connected to the "port expander"? The approach we've taken before
with 5502 designs is to attach a CPLD to a McBSP interface, and then connect various
peripherals to the CPLD. But if the peripherals require high bandwidth, this may not
work.

-Jeff

> Here are the changes from made to the original (fully functional) PCB
> for the revision:
>
> Corrected error: SDRAM was connected to ECLKOUT2, instead connected to
> ECLKOUT1 now.
>
> External clock source was 18.432 MHz, now 12 MHz. (Tested with
> original clock source rate, but still had same limitations)
>
> SDRAM was EDS1232AATA-60, now IS42S32800D-7TL (twice the memory, but
> only half of that is accessible)
>
> Two switching regulators LM2595S-3.3V replaced with one LDO linear
> MCP1826. (Powered from off-board linear without change in functionality)
>
> Mystified,
> John Osmand
> YH, LLC. Start a New Thread