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Hi I have an ADC connceted to one of the McBSPs on the 5510, and I use a DMA channel to transfer words (16 bit) from the data receive register to internal memory. The sample rate generator controls the frame and clock signal generation,and I use the McBSP receive sync event to trigger the transmission. This works fine as long as the DMA channel is configured to transfer data to internal DARAM. The time series sampled from the ADC is very long, and I have to save data in both DARAM and SARAM. I use DMA half frame interrupt to configure the DMA registers for the next DMA transfer. The problem occurs if I set the DMA to transfer data to SARAM, this stops the DMA transfer when the DMA registers are configured for the next DMA frame transfer, which is not a problem if it is set to do the next transfer to DARAM. The transfer actually stops when reconfiguring the DMA registers and not when the transfer to SARAM starts. Thus, it stops after the first half frame transfer to DARAM. Start: - DMA registers configured for transfer to DARAM. First DMA half frame interrupt: - DMA registers reconfigured to do the next transfer (after current frame transfer) to SARAM, AND HERE STOPS THE CURRENT FRAME TRANSFER ! If DMA is reconfigured to use DARAM in stead this does not happen ?!?! Any suggestions ? Best regards Torgeir Jakobsen |
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DMA problem on 5510
Started by ●January 22, 2002
Reply by ●January 23, 20022002-01-23
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Since you're using half-frame interrupt, I assume you're doing
only 1 frame per block and reprogramming the channel config regs for each? First question- couldn't you use multiple frames and the frame index to position your data? Or, for that matter, if your memory buffer could us the end of DARAM and beginning of SARAM, the addresses could just transparently increment thru DARAM into SARAM. At the completion of each block xfer, the DMA channel disables itself. After you've re-loaded the channel config regs, the DMA channel must be re-enabled to copy those "visible" regs into its working versions and be ready for a new xfer. You either do this using "autoinit" or by manually setting the channel enable bit. If you're loading the config regs before the current xfer completes and setting autoinit, I don't see any problems- as soon as the current block finishes, it reloads and enables the channel for the next sync event. But if you're doing it manually, you've copied these new settings at the 1/2 frame mark, but cannot trigger the reload by enabling the channel until after it's been disabled at the end of the current xfer. The spec doesn't say for sure, but writing the the enable at this time could either clobber the working registers in the middle of the xfer (possibly stopping it) or have no effect and the block xfer would complete, and the channel would never be re-enabled. Hope this helps some... George ________________________________________________________________________ Message: 3 Date: Tue, 22 Jan 2002 17:35:03 -0000 From: "torgeirjakobsen" <> Subject: DMA problem on 5510 I have an ADC connceted to one of the McBSPs on the 5510, and I use a DMA channel to transfer words (16 bit) from the data receive register to internal memory. The sample rate generator controls the frame and clock signal generation,and I use the McBSP receive sync event to trigger the transmission. This works fine as long as the DMA channel is configured to transfer data to internal DARAM. The time series sampled from the ADC is very long, and I have to save data in both DARAM and SARAM. I use DMA half frame interrupt to configure the DMA registers for the next DMA transfer. The problem occurs if I set the DMA to transfer data to SARAM, this stops the DMA transfer when the DMA registers are configured for the next DMA frame transfer, which is not a problem if it is set to do the next transfer to DARAM. The transfer actually stops when reconfiguring the DMA registers and not when the transfer to SARAM starts. Thus, it stops after the first half frame transfer to DARAM. Start: - DMA registers configured for transfer to DARAM. First DMA half frame interrupt: - DMA registers reconfigured to do the next transfer (after current frame transfer) to SARAM, AND HERE STOPS THE CURRENT FRAME TRANSFER ! If DMA is reconfigured to use DARAM in stead this does not happen ?!?! Any suggestions ? Best regards Torgeir Jakobsen |
Reply by ●January 24, 20022002-01-24
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Hi Thank you for your suggestions. I use auto-initialization to reconfigure the DMA registers. The REPEAT bit is set to 0, the AUTOINIT bit is set to 1 and the END PROG is set to 0. When all DMA registers are set, the END PROG bit is set to 1, i.e. the next DMA transfer should not start before END PROG is 1 (dependent on REPEAT setting). I could probably do this reconfiguration without using the END PROG bit, since the reconfiguration is done after a half frame which should give plenty of time before the next frame transfer starts. I do not think it is possible to transfer data to both DARAM and SARAM in one frame or block transfer, since the DMA channel has to know the memory type in use (set in DMA_CSDP register). If this was not necessary, I could have used a block transfer (multiple frame) to internal memory. I will try to do the reconfiguration without using auto-initialization. I did a few other tests. The DMA stops if I change the memory from DARAM to SARAM, i.e first frame transfer to DARAM and the second to SARAM. I have also tried to only use SARAM, and the DMA does not stop but I cannot see that the data are saved in SARAM. My first thought was that I can not transfer data to SARAM via DMA at the same time as my program runs from SARAM. I do not think this is the problem, since I am able to transfer data from SARAM without any problems. Best regards Torgeir Jakobsen Senior Engineer, Technology Department Aanderaa Instruments AS e-mail: web: www.aanderaa.com phone; +47 55 10 99 00 direct: +47 55 10 99 77 fax: +47 55 10 99 10 ----- Original Message ----- From: "George Crouse" <> To: <> Sent: Wednesday, January 23, 2002 6:58 PM Subject: [c55x] Re: DMA problem on 5510 > Since you're using half-frame interrupt, I assume you're doing only 1 frame per block and reprogramming the channel config regs for each? First question- couldn't you use multiple frames and the frame index to position your data? Or, for that matter, if your memory buffer could us the end of DARAM and beginning of SARAM, the addresses could just transparently increment thru DARAM into SARAM. > > At the completion of each block xfer, the DMA channel disables itself. After you've re-loaded the channel config regs, the DMA channel must be re-enabled to copy those "visible" regs into its working versions and be ready for a new xfer. You either do this using "autoinit" or by manually setting the channel enable bit. > > If you're loading the config regs before the current xfer completes and setting autoinit, I don't see any problems- as soon as the current block finishes, it reloads and enables the channel for the next sync event. But if you're doing it manually, you've copied these new settings at the 1/2 frame mark, but cannot trigger the reload by enabling the channel until after it's been disabled at the end of the current xfer. The spec doesn't say for sure, but writing the the enable at this time could either clobber the working registers in the middle of the xfer (possibly stopping it) or have no effect and the block xfer would complete, and the channel would never be re-enabled. > > Hope this helps some... > George > > ________________________________________________________________________ > > Message: 3 > Date: Tue, 22 Jan 2002 17:35:03 -0000 > From: "torgeirjakobsen" <> > Subject: DMA problem on 5510 > > I have an ADC connceted to one of the McBSPs on the 5510, and I use a > DMA channel to transfer words (16 bit) from the data receive register > to internal memory. The sample rate generator controls the frame and > clock signal generation,and I use the McBSP receive sync event to > trigger the transmission. This works fine as long as the DMA channel > is configured to transfer data to internal DARAM. > The time series sampled from the ADC is very long, and I have to save > data in both DARAM and SARAM. I use DMA half frame interrupt to > configure the DMA registers for the next DMA transfer. The problem > occurs if I set the DMA to transfer data to SARAM, this stops the DMA > transfer when the DMA registers are configured for the next DMA frame > transfer, which is not a problem if it is set to do the next transfer > to DARAM. The transfer actually stops when reconfiguring the DMA > registers and not when the transfer to SARAM starts. Thus, it stops > after the first half frame transfer to DARAM. > > Start: > - DMA registers configured for transfer to DARAM. > > First DMA half frame interrupt: > - DMA registers reconfigured to do the next transfer (after current > frame transfer) to SARAM, AND HERE STOPS THE CURRENT FRAME TRANSFER ! > If DMA is reconfigured to use DARAM in stead this does not happen ?!?! > > Any suggestions ? > > Best regards > Torgeir Jakobsen > _____________________________________ > Note: If you do a simple "reply" with your email client, only the author of this message will receive your answer. You need to do a "reply all" if you want your answer to be distributed to the entire group. > > _____________________________________ > About this discussion group: > > To Join: Send an email to > > To Post: Send an email to > > To Leave: Send an email to > > Archives: http://www.yahoogroups.com/group/c55x > > Other Groups: http://www.dsprelated.com > > > ">http://docs.yahoo.com/info/terms/ |
Reply by ●January 24, 20022002-01-24
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> I use auto-initialization to reconfigure the DMA registers. The REPEAT
bit is set to 0, the > AUTOINIT bit is set to 1 and the END PROG is set to 0. When all DMA registers are set, the > END PROG bit is set to 1, i.e. the next DMA transfer should not start before END PROG is 1 > (dependent on REPEAT setting). I could probably do this reconfiguration without using the > END PROG bit, since the reconfiguration is done after a half frame which should give plenty of > time before the next frame transfer starts. This all looks good to me. I agree you don't need the END_PROG or REPEAT bits because you have lots of time. You might just try it without using END_PROG, or setting REPEAT=1 just to rule out problems here. > I will try to do the reconfiguration without using auto-initialization. Yeah, you could try interrupting at end-of-frame and reload everything then. Do you have enough time before the next incoming sample? > I do not think it is possible to transfer data to both DARAM and SARAM in one frame or > block transfer, since the DMA channel has to know the memory type in use (set in DMA_CSDP > register). If this was not necessary, I could have used a block transfer (multiple frame) to internal > memory. I didn't read into the datasheet far enough; lots more on-chip memory than the 54xx series I'm using. You're right- you need to set up a new xfer. So you're setting everything up exactly the same except the dest address and mem type (possibly element count)? Are you actually rewriting all the registers (even ones that don't change) and could it matter? Any word/dword alignment issues in that dest address? > I have also tried to only use SARAM, and the DMA does not stop but I cannot see that the data > are saved in SARAM. My first thought was that I can not transfer data to SARAM via DMA > at the same time as my program runs from SARAM. I do not think this is the problem, since I am > able to transfer data from SARAM without any problems. There isn't anything that should prevent this unless DMA can only write to data memory? How does the 55x config those blocks of on-chip mem as program or data? And does the DMA controller care? FWIW, the DMA on the 54xx doesn't care; all it knows is an address. I have both program/data overlayed in the same region and it's just up to me to keep them organized. Last idea- if using the debugger, do you have FREE run bit enabled so the transfers don't stop when you halt the CPU? |
