McBSP in SPI Mode for the TLV320AIC23B Codec
Started by ●January 17, 2006
Hi All,
I'm trying to understand how the McBSP1 (AIC23 Control) is set up for SPI mode in CCS example project dsk_app2.pjt. In this 3-wire configuration the sample rate generator takes the CPU clock (200MHz) and divides it by 100 to get a master SPI clock of 2MHz. To obtain the frame-sync signal, the 2 MHz signal is divided by 20 and has pulse duration of 1 CLKX cycle.
Now, from the McBSP user manual it stated that when the McBSP is in SPI mode or clock stop mode the frame sync width and period is overwritten, is this true?
When I look in the configuration file the frame width is defined as 1 and the frame period is defined as 20 as I stated in the first paragraph. This doesn't make sense for a standard SPI data transfer since the slave enable signal (SS) should be active low during the duration of the transmitted word. It seems that the McBSP SS signal is configured to go active low during the last transmitted bit to latch the code word. I believe this is also stated in the TLV320AIC23B user manual, so the configuration file makes sense.
So I understand that the SS signal's width duration is one clock cycle but why is the period 20 clock cycles?? I want to believe it should be 16 corresponding to the word length, so that the SS signal is active low during the last transmitted bit, right? In Stop Clock mode the FSX and CLKX are both turned off, correct? Any comments would be appreciated
Michael
Reply by ●January 20, 20062006-01-20
hi,
1) yes, in SPI mode, frame sync width and period are
overwritten. Actually the frame sync is generated by
the DXR to XSR copy at master side mcbsp. FSGM=0 for
mcbsp master.
2) i dont have access to the example you are
referring. therefore, i may not comment on that.
anycase, if mcbsp is the master,the FSX can be
connected to /SS to select the spi slave device in 4
wire configuration.
3) you cannot say FSX and CLKX are turned off in spi
mode. actually CLKX is internally connected to the
CLKR signal line of the same mcbsp.
regards,
Dileepan.
--- clarkm2.rpi@clar... wrote:
>
> Hi All,
>
> I'm trying to understand how the McBSP1 (AIC23
> Control) is set up for SPI mode in CCS example
> project dsk_app2.pjt. In this 3-wire configuration
> the sample rate generator takes the CPU clock
> (200MHz) and divides it by 100 to get a master SPI
> clock of 2MHz. To obtain the frame-sync signal, the
> 2 MHz signal is divided by 20 and has pulse duration
> of 1 CLKX cycle.
>
> Now, from the McBSP user manual it stated that when
> the McBSP is in SPI mode or clock stop mode the
> frame sync width and period is overwritten, is this
> true?
>
> When I look in the configuration file the frame
> width is defined as 1 and the frame period is
> defined as 20 as I stated in the first paragraph.
> This doesn't make sense for a standard SPI data
> transfer since the slave enable signal (SS) should
> be active low during the duration of the transmitted
> word. It seems that the McBSP SS signal is
> configured to go active low during the last
> transmitted bit to latch the code word. I believe
> this is also stated in the TLV320AIC23B user manual,
> so the configuration file makes sense.
>
> So I understand that the SS signal's width duration
> is one clock cycle but why is the period 20 clock
> cycles?? I want to believe it should be 16
> corresponding to the word length, so that the SS
> signal is active low during the last transmitted
> bit, right? > In Stop Clock mode the FSX and CLKX are both turned
> off, correct? > Any comments would be appreciated
> Michael >
__________________________________________________
1) yes, in SPI mode, frame sync width and period are
overwritten. Actually the frame sync is generated by
the DXR to XSR copy at master side mcbsp. FSGM=0 for
mcbsp master.
2) i dont have access to the example you are
referring. therefore, i may not comment on that.
anycase, if mcbsp is the master,the FSX can be
connected to /SS to select the spi slave device in 4
wire configuration.
3) you cannot say FSX and CLKX are turned off in spi
mode. actually CLKX is internally connected to the
CLKR signal line of the same mcbsp.
regards,
Dileepan.
--- clarkm2.rpi@clar... wrote:
>
> Hi All,
>
> I'm trying to understand how the McBSP1 (AIC23
> Control) is set up for SPI mode in CCS example
> project dsk_app2.pjt. In this 3-wire configuration
> the sample rate generator takes the CPU clock
> (200MHz) and divides it by 100 to get a master SPI
> clock of 2MHz. To obtain the frame-sync signal, the
> 2 MHz signal is divided by 20 and has pulse duration
> of 1 CLKX cycle.
>
> Now, from the McBSP user manual it stated that when
> the McBSP is in SPI mode or clock stop mode the
> frame sync width and period is overwritten, is this
> true?
>
> When I look in the configuration file the frame
> width is defined as 1 and the frame period is
> defined as 20 as I stated in the first paragraph.
> This doesn't make sense for a standard SPI data
> transfer since the slave enable signal (SS) should
> be active low during the duration of the transmitted
> word. It seems that the McBSP SS signal is
> configured to go active low during the last
> transmitted bit to latch the code word. I believe
> this is also stated in the TLV320AIC23B user manual,
> so the configuration file makes sense.
>
> So I understand that the SS signal's width duration
> is one clock cycle but why is the period 20 clock
> cycles?? I want to believe it should be 16
> corresponding to the word length, so that the SS
> signal is active low during the last transmitted
> bit, right? > In Stop Clock mode the FSX and CLKX are both turned
> off, correct? > Any comments would be appreciated
> Michael >
__________________________________________________
