|
Hi, I am using the C5510 simulator to test my programs and I find that there are a lot of latencies and the final profiling yields a larger clock count than when tested on the hardware board. Is there some setting in CCS that I am missing? thanks, Padma. |
|
|
C5510 simulator48
Started by ●February 1, 2002
Reply by ●February 1, 20022002-02-01
|
Hello Padma, Code Composer Studio ver 1.2 for C5000 is not cycle accurate in the sense that it won't show all the latencies that are there in the code. You need to use cycle accurate simulator (CCS ver 2.0 and up) for knowing the latencies in your code. Also, it is very easy to know where all the potential latencies exist in your code. For this you need to understand the pipeline issues for C55x. Cheers, Suyog. Suyog D. Deshpande Sr. Member of Technical Staff, HelloSoft, Inc. ----Original Message Follows---- From: Padma Raman <> To: Subject: [c55x] C5510 simulator48 Date: Fri, 1 Feb 2002 05:38:49 -0800 (PST) Hi, I am using the C5510 simulator to test my programs and I find that there are a lot of latencies and the final profiling yields a larger clock count than when tested on the hardware board. Is there some setting in CCS that I am missing? thanks, Padma. _________________________________________________________________ MSN Photos is the easiest way to share and print your photos: http://photos.msn.com/support/worldwide.aspx |
Reply by ●February 2, 20022002-02-02
|
Padma Raman <> wrote: >I am using the C5510 simulator to test my programs and >I find that there are a lot of latencies and the final >profiling yields a larger clock count than when tested >on the hardware board. Is there some setting in CCS >that I am missing? I believe the situation with CCS2.1 is this: The c55x simulator models the pipeline latencies correctly but does not attempt to account for memory latency. The 5510 simulator is claimed to model both correctly, but in fact produces complete nonsense. If anyone is succeeding in getting sensible profile results from the 5510 simulator, I would dearly like to know what aspect of your setup differs from mine. Tim. ------------------------ Tim Thorpe Tel: +44 1223 240366 Fax: +44 1223 414402 ------------------------ |
|
|
Reply by ●February 20, 20022002-02-20
|
Hi, I contacted TI regarding this issue. This is the mail I received from them. -Padma. ----Original Message----- From: Rudy Huang from APIC [mailto:] Sent: Monday, February 18, 2002 9:29 AM To: Padmavathi Ramanathan Subject: RE: case#35185630 Dear sir, We have filed a bug entry "SDSsq23897" for the issue. It may be fixed in the next release. The problem is with the implied parallel instruction on c5510 simulator. Implied parallel instruction are taking more cycles on simulator than expected. http://www.ti.com/sc/docs/dsps/hotline/techbits/c55bug.htm#SDSsq23897 Best Regards, Rudy Huang Texas Instruments Email: mailto: Phone: http://www.ti.com/sc/apic Internet: http://www.ti.com/sc/knowledgebase --- In c55x@y..., Tim Thorpe <linux@o...> wrote: > > Padma Raman <padma07_raman@y...> wrote: > > >I am using the C5510 simulator to test my programs and > >I find that there are a lot of latencies and the final > >profiling yields a larger clock count than when tested > >on the hardware board. Is there some setting in CCS > >that I am missing? > > I believe the situation with CCS2.1 is this: > > The c55x simulator models the pipeline latencies correctly > but does not attempt to account for memory latency. > > The 5510 simulator is claimed to model both correctly, but > in fact produces complete nonsense. > > If anyone is succeeding in getting sensible profile results > from the 5510 simulator, I would dearly like to know what > aspect of your setup differs from mine. > > Tim. > ------------------------ > Tim Thorpe Tel: +44 1223 240366 > tim@o... Fax: +44 1223 414402 > ------------------------ |
