McBSP0 as SPI master

Hi,

I have configured McBSP for SPI master operation as specified in the McBSP manual. The SPI slave is a serial flash chip.

When I transmit an 8 bit instruction ("Read Register Status") I see the correct, consistent data, clock and and frame sync signals on the output lines. 8 bit are now ready to be clocked out of the SPI slave.

My question:
Now, how do I send 8 clock cycles on the clock line and retrieve the bits from the slave WITHOUT SENDING any more frame sync pulses (which will be interpreted as new instruction by the slave)?

I tried the csl "Receive16 command" but it does not automatically create clock pulses on the CLKX line.

Any help will be appreciated.

Thanks,

Siva Start a New Thread

hi,

are you sure that the spi slave you are using work
that way? the mcbsp master expects that the slave
start responding as soon as it starts transmitting
data. This is the basic reason why clkx and FSX are
internally shorted to CLKR and FSR.
ANy way one method you can try is to increase the word
length to 16 or 32 such that master generates 16 or 32
clocks for slave. In the 16 bit data, the 8 bit
should be your instruction and the remaining bits
should be zeros. I assume that all zero i not a valid
command for your slave. if yes, use some other bit
pattern for 'filling'. I also assume that your slave
doesnt have problem with incoming unwanted bits while
it shifts out the valid data back to master.

Also refer the following doc and code in the link
below which explains the c6000 mcbsp interface to a
spi ROM. Since the mcbsps are almost same in c6x and
c5x, you can have an idea on how to go about:

http://focus.ti.com/docs/apps/catalog/resources/appnoteabstract.jhtml?abstractName=spra487c

hope this helps,
regards,
Dileepan.

--- s...@shakthi.net wrote:

> Hi,
>
> I have configured McBSP for SPI master operation as
> specified in the McBSP manual. The SPI slave is a
> serial flash chip.
>
> When I transmit an 8 bit instruction ("Read Register
> Status") I see the correct, consistent data, clock
> and and frame sync signals on the output lines. 8
> bit are now ready to be clocked out of the SPI
> slave.
>
> My question:
> Now, how do I send 8 clock cycles on the clock line
> and retrieve the bits from the slave WITHOUT SENDING
> any more frame sync pulses (which will be
> interpreted as new instruction by the slave)?
>
> I tried the csl "Receive16 command" but it does not
> automatically create clock pulses on the CLKX line.
>
> Any help will be appreciated.
>
> Thanks,
>
> Siva
>
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