I too am having unexplained behavior with the DM642 and multiple EDMA channels
that are opened. Whenever we open EDMA channel 9, we see odd behavior in the
CIPRL register - mainly CIP bit for channel 6 is pending even if we have not
opened channel 6.
Anyone else see anything of the sort? Any insight?
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>Hi:
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>Is there a limit on the number of EDMA channels that can be open at a
>time - I understand that the EDMA crossbar processes one at a time,
>but wondering if having too many (say 6-10) user defined EDMA
>channels open on different priority levels can cause any weird
>performance. On a DM642 processor, I find that whenever I open 6 EDMA
>channels, the CIPR bitset never happens !
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>Appreciate any info,
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>Regds
>~ka
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