Hi
C6713 have a setup time and hold time equal 1.5 and 2.5 ns, in PCB design, haw
many delays could be support in data bus and address bus and CLK in external
memory interfaces?
Tanks for your kind support.
Zahra
setup and hold time
Started by ●May 10, 2008
Reply by ●May 10, 20082008-05-10
Zahra-
> C6713 have a setup time and hold time equal 1.5 and 2.5 ns, in PCB design,
> haw many delays could be support in data
> bus and address bus and CLK in external memory interfaces?
I assume you are referring to sync EMIF interface (SDRAM), since you mention CLK signal. Why would you have delays?
Are you putting some other device in between the 6713 and the mem chips?
As long as you keep the SDRAM chips close to the 6713 and use equal-length traces then you should be Ok. With trace
lengths just 30 to 40 mm max you won't have significant PCB delay. I suggest that you download 6713 DSK schematic and
layout files and study them carefully. The DSK is a known-good reference design.
-Jeff
> C6713 have a setup time and hold time equal 1.5 and 2.5 ns, in PCB design,
> haw many delays could be support in data
> bus and address bus and CLK in external memory interfaces?
I assume you are referring to sync EMIF interface (SDRAM), since you mention CLK signal. Why would you have delays?
Are you putting some other device in between the 6713 and the mem chips?
As long as you keep the SDRAM chips close to the 6713 and use equal-length traces then you should be Ok. With trace
lengths just 30 to 40 mm max you won't have significant PCB delay. I suggest that you download 6713 DSK schematic and
layout files and study them carefully. The DSK is a known-good reference design.
-Jeff
Reply by ●May 11, 20082008-05-11
Zahra-
> I used a flash and SDRAM with series resistor, traces length is 3.9cm
> to 7.8cm max.
> Trace length can't be smaller because D0-15 connected to SDRAM then
> to flash.
80 mm is somewhat long but still should be Ok. In any case:
-data line traces between the DSP and SDRAM
should be equal-length
-address line traces between the DSP and SDRAM
should be equal-length
-CLK line should be as long as longest
data/addr line
Trace length and length-matching to the Flash is less important.
> DSK layout is not available for me. I study DSK schematic carefully
> and my design is the same as DSK in flash and SDRAM but My placement
> is different, SDRAM is above of DSP and flash is above of SDRAM.
The DSK boards are intended to serve as complete "reference designs", so the schematic, layout (Gerber) files, and BOM
should all be available. The only exception is that some schematic pages are not released by Spectrum Digital having
to do with their proprietary JTAG-over-USB interface circuitry that is used with CCS software.
If you can't find the layout files for DSK 6713 then you should ask Spectrum Digital and if they can't help then ask
TI hotline.
-Jeff
PS. Why are you posting to me? Post to the group! The only reason anyone answers your question in the first place is
because of the group.
> --- In c..., "Jeff Brower" wrote:
>>
>> Zahra-
>>
>> > C6713 have a setup time and hold time equal 1.5 and 2.5 ns, in
> PCB design,
>> > haw many delays could be support in data
>> > bus and address bus and CLK in external memory interfaces?
>>
>> I assume you are referring to sync EMIF interface (SDRAM), since
> you mention CLK signal. Why would you have delays?
>> Are you putting some other device in between the 6713 and the mem
> chips?
>>
>> As long as you keep the SDRAM chips close to the 6713 and use equal-
> length traces then you should be Ok. With trace
>> lengths just 30 to 40 mm max you won't have significant PCB delay.
> I suggest that you download 6713 DSK schematic and
>> layout files and study them carefully. The DSK is a known-good
> reference design.
>>
>> -Jeff
> I used a flash and SDRAM with series resistor, traces length is 3.9cm
> to 7.8cm max.
> Trace length can't be smaller because D0-15 connected to SDRAM then
> to flash.
80 mm is somewhat long but still should be Ok. In any case:
-data line traces between the DSP and SDRAM
should be equal-length
-address line traces between the DSP and SDRAM
should be equal-length
-CLK line should be as long as longest
data/addr line
Trace length and length-matching to the Flash is less important.
> DSK layout is not available for me. I study DSK schematic carefully
> and my design is the same as DSK in flash and SDRAM but My placement
> is different, SDRAM is above of DSP and flash is above of SDRAM.
The DSK boards are intended to serve as complete "reference designs", so the schematic, layout (Gerber) files, and BOM
should all be available. The only exception is that some schematic pages are not released by Spectrum Digital having
to do with their proprietary JTAG-over-USB interface circuitry that is used with CCS software.
If you can't find the layout files for DSK 6713 then you should ask Spectrum Digital and if they can't help then ask
TI hotline.
-Jeff
PS. Why are you posting to me? Post to the group! The only reason anyone answers your question in the first place is
because of the group.
> --- In c..., "Jeff Brower" wrote:
>>
>> Zahra-
>>
>> > C6713 have a setup time and hold time equal 1.5 and 2.5 ns, in
> PCB design,
>> > haw many delays could be support in data
>> > bus and address bus and CLK in external memory interfaces?
>>
>> I assume you are referring to sync EMIF interface (SDRAM), since
> you mention CLK signal. Why would you have delays?
>> Are you putting some other device in between the 6713 and the mem
> chips?
>>
>> As long as you keep the SDRAM chips close to the 6713 and use equal-
> length traces then you should be Ok. With trace
>> lengths just 30 to 40 mm max you won't have significant PCB delay.
> I suggest that you download 6713 DSK schematic and
>> layout files and study them carefully. The DSK is a known-good
> reference design.
>>
>> -Jeff
