Hey, I'm working at one project on TMS320C6416, and I have one strange
question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I
write to SDRAM in a address, the data in another adrress next 16bytes change all
the time. For example, when I write a data in Ox8000 0000, the data in 0x8000
0010 also change. The operation in 0x8000 0010 also effects Ox8000 0000.
What's the problem?
Thanks very much. And sorry for my poor English.
C6416 SDRAM
Started by ●June 3, 2008
Reply by ●June 3, 20082008-06-03
yangxj_xidian,
On 6/3/08, y...@163.com wrote:
>
> Hey, I'm working at one project on TMS320C6416, and I have one strange
> question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I
> write to SDRAM in a address, the data in another adrress next 16bytes change
> all the time. For example, when I write a data in Ox8000 0000, the data in
> 0x8000 0010 also change. The operation in 0x8000 0010 also effects Ox8000
> 0000. What's the problem?
>
You probably have a problem with an address line - hopefully just a bad
solder joint.
the low part of the address [0x10] = 0001 0000 should be connected to DSP
pins:
EA8-EA7-EA6-EA5 EA4-EA3-x-y [x,y decoded byte enables BE0-3].
I think that your problem is somewhere with EA5 between the DSP and SDRAM.
mikedunn
Thanks very much. And sorry for my poor English.
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On 6/3/08, y...@163.com wrote:
>
> Hey, I'm working at one project on TMS320C6416, and I have one strange
> question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I
> write to SDRAM in a address, the data in another adrress next 16bytes change
> all the time. For example, when I write a data in Ox8000 0000, the data in
> 0x8000 0010 also change. The operation in 0x8000 0010 also effects Ox8000
> 0000. What's the problem?
>
You probably have a problem with an address line - hopefully just a bad
solder joint.
the low part of the address [0x10] = 0001 0000 should be connected to DSP
pins:
EA8-EA7-EA6-EA5 EA4-EA3-x-y [x,y decoded byte enables BE0-3].
I think that your problem is somewhere with EA5 between the DSP and SDRAM.
mikedunn
Thanks very much. And sorry for my poor English.
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●June 4, 20082008-06-04
I check hardware carefully, and there is no wrong.
If I use 16bits sdram, now the addresses count by 8bytes have influence.
ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
What's the possibility?
Thanks again.
If I use 16bits sdram, now the addresses count by 8bytes have influence.
ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
What's the possibility?
Thanks again.
Reply by ●June 4, 20082008-06-04
Hey, I'm working at one project on TMS320C6416, and I have one strange
question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I
write to SDRAM in a address, the data in another adrress next 16bytes change all
the time. For example, when I write a data in Ox8000 0000, the data in 0x8000
0010 also change. The operation in 0x8000 0010 also effects Ox8000 0000.
What's the problem?
>Thanks very much. And sorry for my poor English.
>
>Thanks very much. And sorry for my poor English.
>
Reply by ●June 4, 20082008-06-04
Hey, I'm working at one project on TMS320C6416, and I have one strange
question.I put a 32bits SDRAM on EMIFA, the high 32bits are not used. When I
write to SDRAM in a address, the data in another adrress next 16bytes change all
the time. For example, when I write a data in Ox8000 0000, the data in 0x8000
0010 also change. The operation in 0x8000 0010 also effects Ox8000 0000.
What's the problem?
>Thanks very much. And sorry for my poor English.
>
I check hardware carefully, and there is no wrong.
If I use 16bits sdram, now the addresses count by 8bytes have influence.
ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
My configuration is
static EMIFA_Config MyEmifaConfig {
EMIFA_GBLCTL_RMK
(
EMIFA_GBLCTL_EK2RATE_FULLCLK,
EMIFA_GBLCTL_EK2HZ_CLK,
EMIFA_GBLCTL_EK2EN_ENABLE,
EMIFA_GBLCTL_BRMODE_MRSTATUS,
EMIFA_GBLCTL_NOHOLD_DISABLE,
EMIFA_GBLCTL_EK1HZ_CLK,
EMIFA_GBLCTL_EK1EN_ENABLE,
EMIFA_GBLCTL_CLK4EN_ENABLE,
EMIFA_GBLCTL_CLK6EN_ENABLE
),
0xffffff33, //32BIT SDRAM
0xffffff13,
0xffffff13,
0xffffff13,
EMIFA_SDCTL_RMK
(
EMIFA_SDCTL_SDBSZ_4BANKS,
EMIFA_SDCTL_SDRSZ_12ROW,
EMIFA_SDCTL_SDCSZ_8COL,
EMIFA_SDCTL_RFEN_ENABLE,
EMIFA_SDCTL_INIT_YES, //SDRAM 配置完每个CE空间后，初始化
EMIFA_SDCTL_TRCD_OF(1), //TRCD = 20ns
EMIFA_SDCTL_TRP_OF(1), //TRP = 20ns
EMIFA_SDCTL_TRC_OF(6),
EMIFA_SDCTL_SLFRFR_DISABLE //self refresh mode disable
),
EMIFA_SDTIM_RMK
(
EMIFA_SDTIM_XRFR_DEFAULT, //EXT TIMER default
EMIFA_SDTIM_PERIOD_OF(1560) //64ms, 4096 cycle refresh
),
EMIFA_SDEXT_RMK
(
EMIFA_SDEXT_WR2RD_OF(0), //cycles between write to read command = 1 CLK
EMIFA_SDEXT_WR2DEAC_OF(1), //cycles between write to precharge
EMIFA_SDEXT_WR2WR_OF(0), //cycles between write to write = 1 CLK
EMIFA_SDEXT_R2WDQM_OF(1), //cycles between read to bex = 2 CLK
EMIFA_SDEXT_RD2WR_OF(0), //cycles between read to write = 1 CLK
EMIFA_SDEXT_RD2DEAC_OF(1), //cycles between read to precharge
EMIFA_SDEXT_RD2RD_OF(0), //cycles between read to read = 1 CLK
EMIFA_SDEXT_THZP_OF(0), //Troh = 2 CLK
EMIFA_SDEXT_TWR_OF(1), //Twr >= 1 CLK +7 ns
EMIFA_SDEXT_TRRD_OF(0), //Trrd >= 14ns
EMIFA_SDEXT_TRAS_OF(4), //Tras >= 42ns
EMIFA_SDEXT_TCL_OF(0) //cas latency = 2 CLK
),
0x00000002,
0x00000002,
0x00000002,
0x00000002
};
The clock cycle of SDRAM is 100MHZ.
Is there any wrong?
>Thanks very much. And sorry for my poor English.
>
I check hardware carefully, and there is no wrong.
If I use 16bits sdram, now the addresses count by 8bytes have influence.
ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
My configuration is
static EMIFA_Config MyEmifaConfig {
EMIFA_GBLCTL_RMK
(
EMIFA_GBLCTL_EK2RATE_FULLCLK,
EMIFA_GBLCTL_EK2HZ_CLK,
EMIFA_GBLCTL_EK2EN_ENABLE,
EMIFA_GBLCTL_BRMODE_MRSTATUS,
EMIFA_GBLCTL_NOHOLD_DISABLE,
EMIFA_GBLCTL_EK1HZ_CLK,
EMIFA_GBLCTL_EK1EN_ENABLE,
EMIFA_GBLCTL_CLK4EN_ENABLE,
EMIFA_GBLCTL_CLK6EN_ENABLE
),
0xffffff33, //32BIT SDRAM
0xffffff13,
0xffffff13,
0xffffff13,
EMIFA_SDCTL_RMK
(
EMIFA_SDCTL_SDBSZ_4BANKS,
EMIFA_SDCTL_SDRSZ_12ROW,
EMIFA_SDCTL_SDCSZ_8COL,
EMIFA_SDCTL_RFEN_ENABLE,
EMIFA_SDCTL_INIT_YES, //SDRAM 配置完每个CE空间后，初始化
EMIFA_SDCTL_TRCD_OF(1), //TRCD = 20ns
EMIFA_SDCTL_TRP_OF(1), //TRP = 20ns
EMIFA_SDCTL_TRC_OF(6),
EMIFA_SDCTL_SLFRFR_DISABLE //self refresh mode disable
),
EMIFA_SDTIM_RMK
(
EMIFA_SDTIM_XRFR_DEFAULT, //EXT TIMER default
EMIFA_SDTIM_PERIOD_OF(1560) //64ms, 4096 cycle refresh
),
EMIFA_SDEXT_RMK
(
EMIFA_SDEXT_WR2RD_OF(0), //cycles between write to read command = 1 CLK
EMIFA_SDEXT_WR2DEAC_OF(1), //cycles between write to precharge
EMIFA_SDEXT_WR2WR_OF(0), //cycles between write to write = 1 CLK
EMIFA_SDEXT_R2WDQM_OF(1), //cycles between read to bex = 2 CLK
EMIFA_SDEXT_RD2WR_OF(0), //cycles between read to write = 1 CLK
EMIFA_SDEXT_RD2DEAC_OF(1), //cycles between read to precharge
EMIFA_SDEXT_RD2RD_OF(0), //cycles between read to read = 1 CLK
EMIFA_SDEXT_THZP_OF(0), //Troh = 2 CLK
EMIFA_SDEXT_TWR_OF(1), //Twr >= 1 CLK +7 ns
EMIFA_SDEXT_TRRD_OF(0), //Trrd >= 14ns
EMIFA_SDEXT_TRAS_OF(4), //Tras >= 42ns
EMIFA_SDEXT_TCL_OF(0) //cas latency = 2 CLK
),
0x00000002,
0x00000002,
0x00000002,
0x00000002
};
The clock cycle of SDRAM is 100MHZ.
Is there any wrong?
Reply by ●June 4, 20082008-06-04
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Reply by ●June 4, 20082008-06-04
yangxj,
What you are describing is classic of address lines being shorted together.
>From your description, at least the 0x04 and the 0x08 address lines.
R. Williams
---------- Original Message -----------
From: y...@163.com
To: c...
Sent: Tue, 03 Jun 2008 22:33:55 -0400
Subject: [c6x] Re: C6416 SDRAM
> I check hardware carefully, and there is no wrong.
> If I use 16bits sdram, now the addresses count by 8bytes have influence.
> ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
> If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
> What's the possibility?
> Thanks again.
------- End of Original Message -------
What you are describing is classic of address lines being shorted together.
>From your description, at least the 0x04 and the 0x08 address lines.
R. Williams
---------- Original Message -----------
From: y...@163.com
To: c...
Sent: Tue, 03 Jun 2008 22:33:55 -0400
Subject: [c6x] Re: C6416 SDRAM
> I check hardware carefully, and there is no wrong.
> If I use 16bits sdram, now the addresses count by 8bytes have influence.
> ex, Write to 0x8000 0000, data in 0x8000 0008 also change, vice versa.
> If I use 8bits sdram, 0x8000 0000 and 0x8000 0004 will change simultaneity.
> What's the possibility?
> Thanks again.
------- End of Original Message -------
Reply by ●June 4, 20082008-06-04
yangxj,
OOPS, sorry,
Along with certain address or data lines being shorted,
and what are the possibilities that the incorrect signals are being used for address lines?
a question:
if data is written to address 0x8000 0001 does the data also change at 0x8000 0011?
if so, then it is an address line shorted together or floating.
my suspicion is the address line 0x10 (on 16 bit sdram) is shorted to ground or Vcc
or the wrong signal is being used.
in any case, it is a connection problem between the CPU and the SDRAM.
R. Williams
---------- Original Message -----------
From: y...@163.com
To: c...
Sent: Tue, 03 Jun 2008 22:36:25 -0400
Subject: [c6x] Re: C6416 SDRAM
> Hey, I'm working at one project on TMS320C6416, and I have one strange question.I put a
> 32bits SDRAM on EMIFA, the high 32bits are not used. When I write to SDRAM in a address,
> the data in another adrress next 16bytes change all the time. For example, when I write a
> data in Ox8000 0000, the data in 0x8000 0010 also change. The operation in 0x8000 0010
> also effects Ox8000 0000. What's the problem?
> >Thanks very much. And sorry for my poor English.
> >
>
OOPS, sorry,
Along with certain address or data lines being shorted,
and what are the possibilities that the incorrect signals are being used for address lines?
a question:
if data is written to address 0x8000 0001 does the data also change at 0x8000 0011?
if so, then it is an address line shorted together or floating.
my suspicion is the address line 0x10 (on 16 bit sdram) is shorted to ground or Vcc
or the wrong signal is being used.
in any case, it is a connection problem between the CPU and the SDRAM.
R. Williams
---------- Original Message -----------
From: y...@163.com
To: c...
Sent: Tue, 03 Jun 2008 22:36:25 -0400
Subject: [c6x] Re: C6416 SDRAM
> Hey, I'm working at one project on TMS320C6416, and I have one strange question.I put a
> 32bits SDRAM on EMIFA, the high 32bits are not used. When I write to SDRAM in a address,
> the data in another adrress next 16bytes change all the time. For example, when I write a
> data in Ox8000 0000, the data in 0x8000 0010 also change. The operation in 0x8000 0010
> also effects Ox8000 0000. What's the problem?
> >Thanks very much. And sorry for my poor English.
> >
>
