cache coherence when use dm642?

Hi all,

I have created 32kbyte cache on dm642, and the other part is SRAM.

When i use cpu filled a part of off chip SDRAM(bufferA) with some data, and then i use EDMA to transfer this data from bufferA to a part of on chip SRAM(bufferB), at last i use cpu to copy this data from bufferB to another part of off chip SDRAM(bufferC).

The algorithm was like this,
for(;;)
{
use cpu change the data in bufferA;
CACHE_wbInvL2(bufferA, buffersize, CACHE_WAIT);
CACHE_invL1d(bufferB, buffersize, CACHE_WAIT);
start EDMA transfer from bufferA to bufferB;
use cpu copy data from bufferB to bufferC;
}
In debugging, i have found that the data in bufferA and bufferB are the same, but in bufferC the data have changed and some part of them was the data that have been transferred last time.

I have changed the CACHE_invL1d() into CACHE_wbInvL2() or CACHE_invL2(), but the phenomenon was the same.

Obviously, it is a coherence problem, Anyone who knows how to deal with this issue?
regards
Bing Start a New Thread

Why don't you flush the cache from Buffer B as well, if you do not CPU will keep track of the Buffer B in Cache and as it doesn't know that DMA copied something into it, it doesn't take a look at what's in the memory, just last data from Buffer B that are in Cache. Start a New Thread

Rbmm,

The code sequence is missing the part where the transfer from bufferA to bufferB is completed before
begining the transfer from bufferB to bufferC

R. Williams

---------- Original Message -----------
From: r...@163.com
To: c...
Sent: Fri, 13 Jun 2008 02:54:39 -0400
Subject: [c6x] cache coherence when use dm642?

> Hi all,
>
> I have created 32kbyte cache on dm642, and the other part is SRAM.
>
> When i use cpu filled a part of off chip SDRAM(bufferA) with some data, and then i use
> EDMA to transfer this data from bufferA to a part of on chip SRAM(bufferB), at last i use
> cpu to copy this data from bufferB to another part of off chip SDRAM(bufferC).
>
> The algorithm was like this,
> for(;;)
> {
> use cpu change the data in bufferA;
> CACHE_wbInvL2(bufferA, buffersize, CACHE_WAIT);
> CACHE_invL1d(bufferB, buffersize, CACHE_WAIT);
> start EDMA transfer from bufferA to bufferB;
> use cpu copy data from bufferB to bufferC;
> }
> In debugging, i have found that the data in bufferA and bufferB are the same, but in
> bufferC the data have changed and some part of them was the data that have been
> transferred last time.
>
> I have changed the CACHE_invL1d() into CACHE_wbInvL2() or CACHE_invL2(), but the
> phenomenon was the same.
>
> Obviously, it is a coherence problem, Anyone who knows how to deal with this issue?
>
> regards
> Bing
------- End of Original Message ------- Start a New Thread

Hi R. Williams,

I have look into the spru401.pdf, but i have not found a API fouction to jugde the EDMA complement or not. Can you tell me which founction should i use?
thank you for answer.

Bing

Hi all,
>
>I have created 32kbyte cache on dm642, and the other part is SRAM.
>
>When i use cpu filled a part of off chip SDRAM(bufferA) with some data, and then i use EDMA to transfer this data from bufferA to a part of on chip SRAM(bufferB), at last i use cpu to copy this data from bufferB to another part of off chip SDRAM(bufferC).
>
>The algorithm was like this,
>for(;;)
>{
> use cpu change the data in bufferA;
> CACHE_wbInvL2(bufferA, buffersize, CACHE_WAIT);
> CACHE_invL1d(bufferB, buffersize, CACHE_WAIT);
> start EDMA transfer from bufferA to bufferB;
> use cpu copy data from bufferB to bufferC;
>}
>In debugging, i have found that the data in bufferA and bufferB are the same, but in bufferC the data have changed and some part of them was the data that have been transferred last time.
>
>I have changed the CACHE_invL1d() into CACHE_wbInvL2() or CACHE_invL2(), but the phenomenon was the same.
>
>Obviously, it is a coherence problem, Anyone who knows how to deal with this issue?
>regards
>Bing
> Start a New Thread

Hi all,

In recently debugging, i found that when i changed the scrouce and destination address into 2D, but it will transfer some redundancy data , then the result will right but the 1D will not right.

Bing Start a New Thread