Hi,
I have successfully implemented a second-level DSP/BIOS bootloader on C6711D
and my application works well. The problem is that the first sector of the flash
is erased after some time. Only the first value is random while the rest are FF.
This time may vary from days to months.
The DSP relies on the IPU/IPD for its default boot mode – 8 bit
asynchronous flash.
I have observed (at the scope) 4 writing operations after the copy of the first
1k into the internal memory. These write operations occur 1 micro second after
the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they
are surely not as a result from the bootloader instructions. The strange part is
that these writing operations seems to be at random space. I have observed them
many times after the reset and transferring the bootloader into the internal
ram. Therefore I am ordering them with the bigger probability to occur at the
top:
4 writing operations at CE0 space - external RAM
4 writing operations at CE3 space – not used in my board
no writing operations – which is correct
I did not observed writing operations at CE1 and CE2, but I suppose that the
corrupted flash is because of writing at CE1.
During these write operations the addresses, data and CE signals are not
changing. However they are not the same after each reset. Most often EA4 is
varying and some others too.
Do you have any idea why the DSP performs these 4 writes? I did not find any
description of such a behavior in its documentation! At least give me some
suggestions to clear this problem.
Thank you in advance!
Dragomir Nikolov
Undesired flash writing after bootloading
Started by ●June 15, 2008
Reply by ●June 16, 20082008-06-16
dragon,
flash is not writable with out a complex, carefully timed sequence of instructions.
a program should be able to write to flash (with simple writes) all day with out any effect to the
flash.
to me, the symptoms you describe are indicative of a defective chip.
R. Williams
---------- Original Message -----------
From: d...@yahoo.com
To: c...
Sent: Sun, 15 Jun 2008 17:24:14 -0400
Subject: [c6x] Undesired flash writing after bootloading
> Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my
> application works well. The problem is that the first sector of the flash is erased after
> some time. Only the first value is random while the rest are FF. This time may vary from
> days to months. The DSP relies on the IPU/IPD for its default boot mode – 8 bit
> asynchronous flash. I have observed (at the scope) 4 writing operations after the copy of
> the first 1k into the internal memory. These write operations occur 1 micro second after
> the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely
> not as a result from the bootloader instructions. The strange part is that these writing
> operations seems to be at random space. I have observed them many times after the reset
> and transferring the bootloader into the internal ram. Therefore I am ordering them with
> the bigger probability to occur at the top: 4 writing operations at CE0 space - external
> RAM 4 writing operations at CE3 space – not used in my board no writing operations –
> which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted
> flash is because of writing at CE1. During these write operations the addresses, data and
> CE signals are not changing. However they are not the same after each reset. Most often
> EA4 is varying and some others too. Do you have any idea why the DSP performs these 4
> writes? I did not find any description of such a behavior in its documentation! At least
> give me some suggestions to clear this problem.
>
> Thank you in advance!
>
> Dragomir Nikolov
>
flash is not writable with out a complex, carefully timed sequence of instructions.
a program should be able to write to flash (with simple writes) all day with out any effect to the
flash.
to me, the symptoms you describe are indicative of a defective chip.
R. Williams
---------- Original Message -----------
From: d...@yahoo.com
To: c...
Sent: Sun, 15 Jun 2008 17:24:14 -0400
Subject: [c6x] Undesired flash writing after bootloading
> Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my
> application works well. The problem is that the first sector of the flash is erased after
> some time. Only the first value is random while the rest are FF. This time may vary from
> days to months. The DSP relies on the IPU/IPD for its default boot mode – 8 bit
> asynchronous flash. I have observed (at the scope) 4 writing operations after the copy of
> the first 1k into the internal memory. These write operations occur 1 micro second after
> the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely
> not as a result from the bootloader instructions. The strange part is that these writing
> operations seems to be at random space. I have observed them many times after the reset
> and transferring the bootloader into the internal ram. Therefore I am ordering them with
> the bigger probability to occur at the top: 4 writing operations at CE0 space - external
> RAM 4 writing operations at CE3 space – not used in my board no writing operations –
> which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted
> flash is because of writing at CE1. During these write operations the addresses, data and
> CE signals are not changing. However they are not the same after each reset. Most often
> EA4 is varying and some others too. Do you have any idea why the DSP performs these 4
> writes? I did not find any description of such a behavior in its documentation! At least
> give me some suggestions to clear this problem.
>
> Thank you in advance!
>
> Dragomir Nikolov
>
Reply by ●June 16, 20082008-06-16
Hi,
I know about the complexity of the writing procedure with the specific keys at certain addresses. This is another one reason that I am confused about the situation. The problem is the same with all of the 15 chips I have (AT29LV010A, AT29LV020 and AT29LV040A). It is not possible that all chips from three series to be defective.
In fact I can achieve the same effect (FF in the whole sector and specific value at a given address). I just have to use CCS to change the value of any address within the flash memory space (double click, typing the value, and then ‘enter’), but if you repeat it at the next address you get the sector erased again. That is why I am sure that if these 4 writing operations occur at CE1, the sector is erased and the value of the specific address is set to the random databus at that moment.
Anyway I still need an explanation how to prevent these 4 write operations at the end of the bootloader copy.
Thank you for the reply
Dragomir Nikolov
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
I know about the complexity of the writing procedure with the specific keys at certain addresses. This is another one reason that I am confused about the situation. The problem is the same with all of the 15 chips I have (AT29LV010A, AT29LV020 and AT29LV040A). It is not possible that all chips from three series to be defective.
In fact I can achieve the same effect (FF in the whole sector and specific value at a given address). I just have to use CCS to change the value of any address within the flash memory space (double click, typing the value, and then ‘enter’), but if you repeat it at the next address you get the sector erased again. That is why I am sure that if these 4 writing operations occur at CE1, the sector is erased and the value of the specific address is set to the random databus at that moment.
Anyway I still need an explanation how to prevent these 4 write operations at the end of the bootloader copy.
Thank you for the reply
Dragomir Nikolov
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
Reply by ●June 16, 20082008-06-16
Dragomir-
> I have successfully implemented a second-level DSP/BIOS bootloader
> on C6711D and my application works well. The problem is that the first
> sector of the flash is erased after some time. Only the first value is
> random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8
> bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the
> copy of the first 1k into the internal memory. These write operations
> occur 1 micro second after the copy of the bootloader (the DSP clock
> frequency is 50 MHz). Therefore they are surely not as a result from
> the bootloader instructions. The strange part is that these writing
> operations seems to be at random space. I have observed them many times
> after the reset and transferring the bootloader into the internal ram.
> Therefore I am ordering them with the bigger probability to occur at
> the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I
> suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE
> signals are not changing. However they are not the same after each
> reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes?
> I did not find any description of such a behavior in its
> documentation! At least give me some suggestions to clear this
> problem.
Since you say this always happens (not intermittent), and you you know it's about 1
usec after the bootloader 1k copy, then why don't you just use CCS + emulator and
single-step your code until you see a write strobe on the scope? Where is the code
when it happens?
-Jeff
> I have successfully implemented a second-level DSP/BIOS bootloader
> on C6711D and my application works well. The problem is that the first
> sector of the flash is erased after some time. Only the first value is
> random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8
> bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the
> copy of the first 1k into the internal memory. These write operations
> occur 1 micro second after the copy of the bootloader (the DSP clock
> frequency is 50 MHz). Therefore they are surely not as a result from
> the bootloader instructions. The strange part is that these writing
> operations seems to be at random space. I have observed them many times
> after the reset and transferring the bootloader into the internal ram.
> Therefore I am ordering them with the bigger probability to occur at
> the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I
> suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE
> signals are not changing. However they are not the same after each
> reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes?
> I did not find any description of such a behavior in its
> documentation! At least give me some suggestions to clear this
> problem.
Since you say this always happens (not intermittent), and you you know it's about 1
usec after the bootloader 1k copy, then why don't you just use CCS + emulator and
single-step your code until you see a write strobe on the scope? Where is the code
when it happens?
-Jeff
Reply by ●June 17, 20082008-06-17
I think I was not clear enough. The writings do not happen all the time (after
each reset of the DSP). They occur randomly and in random space, however more
often in CE0. These writings are caused by the DSP and they do not depend of the
bootloader program. They persist even if the flash memory chip is removed from
the board.
That is why I am asking for some help in order to explain how the DSP provokes this problem. Maybe it is some strange boot configuration or DSP option?
I will be thankful for any advice!
Dragomir Nikolov
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
That is why I am asking for some help in order to explain how the DSP provokes this problem. Maybe it is some strange boot configuration or DSP option?
I will be thankful for any advice!
Dragomir Nikolov
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
Reply by ●June 17, 20082008-06-17
Hi,
do you have any code in your application that is able to write/erase the
flash? Maybe something run berserk and this code is executed.
How do you program your flash? In circuit or by programmer? Maybe you
can use protection features of you flash.
HTH
Gustl
d...@yahoo.com schrieb:
> I think I was not clear enough. The writings do not happen all the
> time (after each reset of the DSP). They occur randomly and in random
> space, however more often in CE0. These writings are caused by the
> DSP and they do not depend of the bootloader program. They persist
> even if the flash memory chip is removed from the board. That is why
> I am asking for some help in order to explain how the DSP provokes
> this problem. Maybe it is some strange boot configuration or DSP
> option? I will be thankful for any advice!
>
> Dragomir Nikolov
> Hi,
>> I have successfully implemented a second-level DSP/BIOS bootloader
>> on C6711D and my application works well. The problem is that the
>> first sector of the flash is erased after some time. Only the first
>> value is random while the rest are FF. This time may vary from days
>> to months. The DSP relies on the IPU/IPD for its default boot mode
>> ? 8 bit asynchronous flash. I have observed (at the scope) 4
>> writing operations after the copy of the first 1k into the internal
>> memory. These write operations occur 1 micro second after the copy
>> of the bootloader (the DSP clock frequency is 50 MHz). Therefore
>> they are surely not as a result from the bootloader instructions.
>> The strange part is that these writing operations seems to be at
>> random space. I have observed them many times after the reset and
>> transferring the bootloader into the internal ram. Therefore I am
>> ordering them with the bigger probability to occur at the top: 4
>> writing operations at CE0 space - external RAM 4 writing
>> operations at CE3 space ? not used in my board no writing
>> operations ? which is correct I did not observed writing
>> operations at CE1 and CE2, but I suppose that the corrupted flash
>> is because of writing at CE1. During these write operations the
>> addresses, data and CE signals are not changing. However they are
>> not the same after each reset. Most often EA4 is varying and some
>> others too. Do you have any idea why the DSP performs these 4
>> writes? I did not find any description of such a behavior in its
>> documentation! At least give me some suggestions to clear this
>> problem.
>>
>> Thank you in advance!
>>
>> Dragomir Nikolov
>
do you have any code in your application that is able to write/erase the
flash? Maybe something run berserk and this code is executed.
How do you program your flash? In circuit or by programmer? Maybe you
can use protection features of you flash.
HTH
Gustl
d...@yahoo.com schrieb:
> I think I was not clear enough. The writings do not happen all the
> time (after each reset of the DSP). They occur randomly and in random
> space, however more often in CE0. These writings are caused by the
> DSP and they do not depend of the bootloader program. They persist
> even if the flash memory chip is removed from the board. That is why
> I am asking for some help in order to explain how the DSP provokes
> this problem. Maybe it is some strange boot configuration or DSP
> option? I will be thankful for any advice!
>
> Dragomir Nikolov
> Hi,
>> I have successfully implemented a second-level DSP/BIOS bootloader
>> on C6711D and my application works well. The problem is that the
>> first sector of the flash is erased after some time. Only the first
>> value is random while the rest are FF. This time may vary from days
>> to months. The DSP relies on the IPU/IPD for its default boot mode
>> ? 8 bit asynchronous flash. I have observed (at the scope) 4
>> writing operations after the copy of the first 1k into the internal
>> memory. These write operations occur 1 micro second after the copy
>> of the bootloader (the DSP clock frequency is 50 MHz). Therefore
>> they are surely not as a result from the bootloader instructions.
>> The strange part is that these writing operations seems to be at
>> random space. I have observed them many times after the reset and
>> transferring the bootloader into the internal ram. Therefore I am
>> ordering them with the bigger probability to occur at the top: 4
>> writing operations at CE0 space - external RAM 4 writing
>> operations at CE3 space ? not used in my board no writing
>> operations ? which is correct I did not observed writing
>> operations at CE1 and CE2, but I suppose that the corrupted flash
>> is because of writing at CE1. During these write operations the
>> addresses, data and CE signals are not changing. However they are
>> not the same after each reset. Most often EA4 is varying and some
>> others too. Do you have any idea why the DSP performs these 4
>> writes? I did not find any description of such a behavior in its
>> documentation! At least give me some suggestions to clear this
>> problem.
>>
>> Thank you in advance!
>>
>> Dragomir Nikolov
>
Reply by ●June 17, 20082008-06-17
Dragomir,
On 6/17/08, d...@yahoo.com wrote:
> I think I was not clear enough. The writings do not happen all the time (after each reset of the DSP). They occur randomly and in random space, however more often in CE0. These writings are caused by the DSP and they do not depend of the bootloader program. They persist even if the flash memory chip is removed from the board.
> That is why I am asking for some help in order to explain how the DSP provokes this problem. Maybe it is some strange boot configuration or DSP option?
> I will be thankful for any advice!
First I will start with a fact [as I understand it]:
1. Any time that you reset a 6711 device [EXCEPT in HPI boot mode],
the DSP will 'fetch and try to execute something'. This will happen
even if there are no external memory devices connected.
2. Try your test with the device in HPI boot mode to ensure that the
signals are not occuring during reset.
3. Embed a software breakpoint in flash [ asm( .word 0x10000000); ]
just before you branch to internal RAM. Perform resets and run to
breakpoint. Repeat and observe your problem signals. *Do NOT use a GEL
file*
NOTE: You must have an emulator connected for the DSP to recognize the
sw bp. You may be able to issue 'run free' from CCS and keep reseting
the device.
4. Have you seen strobes yet??
5. If no, remove the embedded sw bp.
6. You will probably have to use AET to catch your error. Let me know
if you get here.
FYI - I have worked on a few 6211/6711/6713 boards - some of which
have been reset many thousands of times and others that have run for
extended periods of time. I have never seen a Flash corruption
problem that was not due to defective hardware or software.
7. Have you monitored your power supply with a scope??
mikedunn
>
> Dragomir Nikolov
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space not used in my board
> > no writing operations which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
> >
> > Dragomir Nikolov
>
>
>
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On 6/17/08, d...@yahoo.com wrote:
> I think I was not clear enough. The writings do not happen all the time (after each reset of the DSP). They occur randomly and in random space, however more often in CE0. These writings are caused by the DSP and they do not depend of the bootloader program. They persist even if the flash memory chip is removed from the board.
> That is why I am asking for some help in order to explain how the DSP provokes this problem. Maybe it is some strange boot configuration or DSP option?
> I will be thankful for any advice!
First I will start with a fact [as I understand it]:
1. Any time that you reset a 6711 device [EXCEPT in HPI boot mode],
the DSP will 'fetch and try to execute something'. This will happen
even if there are no external memory devices connected.
2. Try your test with the device in HPI boot mode to ensure that the
signals are not occuring during reset.
3. Embed a software breakpoint in flash [ asm( .word 0x10000000); ]
just before you branch to internal RAM. Perform resets and run to
breakpoint. Repeat and observe your problem signals. *Do NOT use a GEL
file*
NOTE: You must have an emulator connected for the DSP to recognize the
sw bp. You may be able to issue 'run free' from CCS and keep reseting
the device.
4. Have you seen strobes yet??
5. If no, remove the embedded sw bp.
6. You will probably have to use AET to catch your error. Let me know
if you get here.
FYI - I have worked on a few 6211/6711/6713 boards - some of which
have been reset many thousands of times and others that have run for
extended periods of time. I have never seen a Flash corruption
problem that was not due to defective hardware or software.
7. Have you monitored your power supply with a scope??
mikedunn
>
> Dragomir Nikolov
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space not used in my board
> > no writing operations which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
> >
> > Dragomir Nikolov
>
>
>
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●June 17, 20082008-06-17
Dragomir-
> I think I was not clear enough. The writings do not happen all the time
> (after each reset of the DSP). They occur randomly and in random space,
> however more often in CE0. These writings are caused by the DSP and
> they do not depend of the bootloader program. They persist even if the
> flash memory chip is removed from the board.
> That is why I am asking for some help in order to explain how the DSP
> provokes this problem.
You say "randomly" -- how often? For what (approx) percentage of reset/boot do the
write strobes occur?
> Maybe it is some strange boot configuration or DSP option?
Maybe, but more likely it's your code, something like an uninitialized pointer, or
pipeline violation.
> I will be thankful for any advice!
Use CCS + emulator, allow your code to run until after the 1k boot copy (Mike's
suggestion is a sw breakpoint), then single-step your code until you see a write
strobe on the scope. Then you know exactly what code committed the crime.
Yes that's tedious and could take a while, but you won't debug this by guessing at
it.
-Jeff
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space – not used in my board
> > no writing operations – which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
> I think I was not clear enough. The writings do not happen all the time
> (after each reset of the DSP). They occur randomly and in random space,
> however more often in CE0. These writings are caused by the DSP and
> they do not depend of the bootloader program. They persist even if the
> flash memory chip is removed from the board.
> That is why I am asking for some help in order to explain how the DSP
> provokes this problem.
You say "randomly" -- how often? For what (approx) percentage of reset/boot do the
write strobes occur?
> Maybe it is some strange boot configuration or DSP option?
Maybe, but more likely it's your code, something like an uninitialized pointer, or
pipeline violation.
> I will be thankful for any advice!
Use CCS + emulator, allow your code to run until after the 1k boot copy (Mike's
suggestion is a sw breakpoint), then single-step your code until you see a write
strobe on the scope. Then you know exactly what code committed the crime.
Yes that's tedious and could take a while, but you won't debug this by guessing at
it.
-Jeff
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space – not used in my board
> > no writing operations – which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
Reply by ●June 19, 20082008-06-19
Hi,
Thank you for the advices! With your help I have identified the piece of code that is causing the problem. I am still not sure if it is a hardware or software problem, but it is provoked by the software. I have found the piece of code by inserting endless loops in the software and then observing the result.
The flash got corrupted after this line:
if (Proto_CPLD_Input_SW1==1)
Unfortunately I can not understand why this comparison erases the flash. The CCS is not showing me any code, after this command line, when I switch on “view mixed source/asm”.
The integer variable Proto_CPLD_Input_SW1 initializes its value by the following commands:
io_port_values=*(unsigned volatile int *)IO_PORT;
Proto_CPLD_Input_SW1=(io_port_values&0x0400000)==0;
The above ones are the same in any DSK example, which is making me confused why my flash is erased.
I will be grateful if you give me any ideas?
Thank you in advance
Drago
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
Thank you for the advices! With your help I have identified the piece of code that is causing the problem. I am still not sure if it is a hardware or software problem, but it is provoked by the software. I have found the piece of code by inserting endless loops in the software and then observing the result.
The flash got corrupted after this line:
if (Proto_CPLD_Input_SW1==1)
Unfortunately I can not understand why this comparison erases the flash. The CCS is not showing me any code, after this command line, when I switch on “view mixed source/asm”.
The integer variable Proto_CPLD_Input_SW1 initializes its value by the following commands:
io_port_values=*(unsigned volatile int *)IO_PORT;
Proto_CPLD_Input_SW1=(io_port_values&0x0400000)==0;
The above ones are the same in any DSK example, which is making me confused why my flash is erased.
I will be grateful if you give me any ideas?
Thank you in advance
Drago
Hi,
> I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> The DSP relies on the IPU/IPD for its default boot mode – 8 bit asynchronous flash.
> I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> 4 writing operations at CE0 space - external RAM
> 4 writing operations at CE3 space – not used in my board
> no writing operations – which is correct
>
> I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
>
>Thank you in advance!
>
> Dragomir Nikolov
Reply by ●June 19, 20082008-06-19
Drago,
On 6/19/08, d...@yahoo.com wrote:
> Hi,
> Thank you for the advices! With your help I have identified the piece of code that is causing the problem. I am still not sure if it is a hardware or software problem, but it is provoked by the software. I have found the piece of code by inserting endless loops in the software and then observing the result.
> The flash got corrupted after this line:
> if (Proto_CPLD_Input_SW1==1)
> Unfortunately I can not understand why this comparison erases the flash. The CCS is not showing me any code, after this command line, when I switch on "view mixed source/asm".
> The integer variable Proto_CPLD_Input_SW1 initializes its value by the following commands:
> io_port_values=*(unsigned volatile int *)IO_PORT;
> Proto_CPLD_Input_SW1=(io_port_values&0x0400000)==0;
> The above ones are the same in any DSK example, which is making me confused why my flash is erased.
> I will be grateful if you give me any ideas?
Do you remember your original assumption?? [I am not sure exactly what
was in your mind]
One of the greatest difficulties when troubleshooting hard problems is
that we make assumptions and assume them as facts without realizing
it.
Also, never assume that something works just because it came from an example.
I assume that 'SW1' is not important for testing/debugging at this
point. Comment out the I/O lines of code and replace it with hardcoded
values that you expect.
Can you control the problem by switching between 'hard coded' and 'I/O
determined' SW values?? If yes, your FPGA may be 'helping you more
than you realize' :-)
mikedunn
>
> Thank you in advance
> Drago
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space not used in my board
> > no writing operations which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
> >
> > Dragomir Nikolov
>
> >
> >
>
>
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On 6/19/08, d...@yahoo.com wrote:
> Hi,
> Thank you for the advices! With your help I have identified the piece of code that is causing the problem. I am still not sure if it is a hardware or software problem, but it is provoked by the software. I have found the piece of code by inserting endless loops in the software and then observing the result.
> The flash got corrupted after this line:
> if (Proto_CPLD_Input_SW1==1)
> Unfortunately I can not understand why this comparison erases the flash. The CCS is not showing me any code, after this command line, when I switch on "view mixed source/asm".
> The integer variable Proto_CPLD_Input_SW1 initializes its value by the following commands:
> io_port_values=*(unsigned volatile int *)IO_PORT;
> Proto_CPLD_Input_SW1=(io_port_values&0x0400000)==0;
> The above ones are the same in any DSK example, which is making me confused why my flash is erased.
> I will be grateful if you give me any ideas?
Do you remember your original assumption?? [I am not sure exactly what
was in your mind]
One of the greatest difficulties when troubleshooting hard problems is
that we make assumptions and assume them as facts without realizing
it.
Also, never assume that something works just because it came from an example.
I assume that 'SW1' is not important for testing/debugging at this
point. Comment out the I/O lines of code and replace it with hardcoded
values that you expect.
Can you control the problem by switching between 'hard coded' and 'I/O
determined' SW values?? If yes, your FPGA may be 'helping you more
than you realize' :-)
mikedunn
>
> Thank you in advance
> Drago
> Hi,
> > I have successfully implemented a second-level DSP/BIOS bootloader on C6711D and my application works well. The problem is that the first sector of the flash is erased after some time. Only the first value is random while the rest are FF. This time may vary from days to months.
> > The DSP relies on the IPU/IPD for its default boot mode 8 bit asynchronous flash.
> > I have observed (at the scope) 4 writing operations after the copy of the first 1k into the internal memory. These write operations occur 1 micro second after the copy of the bootloader (the DSP clock frequency is 50 MHz). Therefore they are surely not as a result from the bootloader instructions. The strange part is that these writing operations seems to be at random space. I have observed them many times after the reset and transferring the bootloader into the internal ram. Therefore I am ordering them with the bigger probability to occur at the top:
> > 4 writing operations at CE0 space - external RAM
> > 4 writing operations at CE3 space not used in my board
> > no writing operations which is correct
> >
> > I did not observed writing operations at CE1 and CE2, but I suppose that the corrupted flash is because of writing at CE1.
> > During these write operations the addresses, data and CE signals are not changing. However they are not the same after each reset. Most often EA4 is varying and some others too.
> > Do you have any idea why the DSP performs these 4 writes? I did not find any description of such a behavior in its documentation! At least give me some suggestions to clear this problem.
> >
> >Thank you in advance!
> >
> > Dragomir Nikolov
>
> >
> >
>
>
>
>
>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
