Hi all,
I have a peripheral device that was designed to run with an EMIF
frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
down to 100MHz via the on-board dip switches, but those switches also
brings down CPU frequency. I want the CPU frequency to remain the same
(1Ghz).
I already did a search in the archives here and what I have tried so
far is to adjust some values in the DSP/BIOS config file. I tried
changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
really help but am I headed in the right direction?
My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
space.
Thanks,
Charley
EMIF Frequency on the 6416 DSK
Started by ●July 21, 2008
Reply by ●July 21, 20082008-07-21
The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
behaves as a slave to the DSP and connects to the external memory
interface and external perpipheral interface connectors.
I thought it was an asychronous device, but when I set the board to
600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
work. I also know by speaking to the manufacturer (Avnet), the board
was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
and I was hoping to bring down the EMIFA frequency seperately. Is this
possible?
Thanks
On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> Charley-
>
>> I have a peripheral device that was designed to run with an EMIF
>> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
>> down to 100MHz via the on-board dip switches, but those switches also
>> brings down CPU frequency. I want the CPU frequency to remain the same
>> (1Ghz).
>>
>> I already did a search in the archives here and what I have tried so
>> far is to adjust some values in the DSP/BIOS config file. I tried
>> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
>> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
>> really help but am I headed in the right direction?
>>
>> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
>> space.
>
> What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> contains asynchronous devices or interfaces, then clock doesn't matter.
>
> -Jeff
>
behaves as a slave to the DSP and connects to the external memory
interface and external perpipheral interface connectors.
I thought it was an asychronous device, but when I set the board to
600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
work. I also know by speaking to the manufacturer (Avnet), the board
was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
and I was hoping to bring down the EMIFA frequency seperately. Is this
possible?
Thanks
On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> Charley-
>
>> I have a peripheral device that was designed to run with an EMIF
>> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
>> down to 100MHz via the on-board dip switches, but those switches also
>> brings down CPU frequency. I want the CPU frequency to remain the same
>> (1Ghz).
>>
>> I already did a search in the archives here and what I have tried so
>> far is to adjust some values in the DSP/BIOS config file. I tried
>> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
>> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
>> really help but am I headed in the right direction?
>>
>> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
>> space.
>
> What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> contains asynchronous devices or interfaces, then clock doesn't matter.
>
> -Jeff
>
Reply by ●July 21, 20082008-07-21
Charley-
> I have a peripheral device that was designed to run with an EMIF
> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> down to 100MHz via the on-board dip switches, but those switches also
> brings down CPU frequency. I want the CPU frequency to remain the same
> (1Ghz).
>
> I already did a search in the archives here and what I have tried so
> far is to adjust some values in the DSP/BIOS config file. I tried
> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> really help but am I headed in the right direction?
>
> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> space.
What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
contains asynchronous devices or interfaces, then clock doesn't matter.
-Jeff
> I have a peripheral device that was designed to run with an EMIF
> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> down to 100MHz via the on-board dip switches, but those switches also
> brings down CPU frequency. I want the CPU frequency to remain the same
> (1Ghz).
>
> I already did a search in the archives here and what I have tried so
> far is to adjust some values in the DSP/BIOS config file. I tried
> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> really help but am I headed in the right direction?
>
> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> space.
What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
contains asynchronous devices or interfaces, then clock doesn't matter.
-Jeff
Reply by ●July 21, 20082008-07-21
Charley-
> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
> behaves as a slave to the DSP and connects to the external memory
> interface and external perpipheral interface connectors.
>
> I thought it was an asychronous device, but when I set the board to
> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
> work.
Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related clock
(signal named ECLKOUT or similar) used for anything? If so, then it could be
synchronous, depending on where the signal is routed on the daughtercard. If not,
then it's an asynchronous interface and your DSP EMIF registers should be set up
appropriately.
In the data sheet (see comments below), there is an IFCONFIG Register that has a bit
set for ASYNC or SYNC operation. During normal (working) operation, what is that bit
set to?
> I also know by speaking to the manufacturer (Avnet), the board
> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
> and I was hoping to bring down the EMIFA frequency seperately. Is this
> possible?
Cypress has evidently obsoleted the CY7C68001 device, but I found this data sheet:
http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
On page 13, it discusses internal vs. external clock. It could be that the
daughtercard uses an external clock from the DSK board in order to derive or comply
with correct USB bus timings, so if you deviate then things fall apart. But I would
think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't be used
with a wide range of DSK boards.
Another possibility is an issue with software that Avnet provides for the DSK6416 DSK
-- some timing loop or other code that depends on a 600 MHz clock. Not sure, just
some guesses...
-Jeff
> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> > Charley-
> >
> >> I have a peripheral device that was designed to run with an EMIF
> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> >> down to 100MHz via the on-board dip switches, but those switches also
> >> brings down CPU frequency. I want the CPU frequency to remain the same
> >> (1Ghz).
> >>
> >> I already did a search in the archives here and what I have tried so
> >> far is to adjust some values in the DSP/BIOS config file. I tried
> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> >> really help but am I headed in the right direction?
> >>
> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> >> space.
> >
> > What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> > contains asynchronous devices or interfaces, then clock doesn't matter.
> >
> > -Jeff
> >
> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
> behaves as a slave to the DSP and connects to the external memory
> interface and external perpipheral interface connectors.
>
> I thought it was an asychronous device, but when I set the board to
> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
> work.
Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related clock
(signal named ECLKOUT or similar) used for anything? If so, then it could be
synchronous, depending on where the signal is routed on the daughtercard. If not,
then it's an asynchronous interface and your DSP EMIF registers should be set up
appropriately.
In the data sheet (see comments below), there is an IFCONFIG Register that has a bit
set for ASYNC or SYNC operation. During normal (working) operation, what is that bit
set to?
> I also know by speaking to the manufacturer (Avnet), the board
> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
> and I was hoping to bring down the EMIFA frequency seperately. Is this
> possible?
Cypress has evidently obsoleted the CY7C68001 device, but I found this data sheet:
http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
On page 13, it discusses internal vs. external clock. It could be that the
daughtercard uses an external clock from the DSK board in order to derive or comply
with correct USB bus timings, so if you deviate then things fall apart. But I would
think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't be used
with a wide range of DSK boards.
Another possibility is an issue with software that Avnet provides for the DSK6416 DSK
-- some timing loop or other code that depends on a 600 MHz clock. Not sure, just
some guesses...
-Jeff
> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> > Charley-
> >
> >> I have a peripheral device that was designed to run with an EMIF
> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> >> down to 100MHz via the on-board dip switches, but those switches also
> >> brings down CPU frequency. I want the CPU frequency to remain the same
> >> (1Ghz).
> >>
> >> I already did a search in the archives here and what I have tried so
> >> far is to adjust some values in the DSP/BIOS config file. I tried
> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> >> really help but am I headed in the right direction?
> >>
> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> >> space.
> >
> > What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> > contains asynchronous devices or interfaces, then clock doesn't matter.
> >
> > -Jeff
> >
Reply by ●July 21, 20082008-07-21
Charley-
> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
> behaves as a slave to the DSP and connects to the external memory
> interface and external perpipheral interface connectors.
>
> I thought it was an asychronous device, but when I set the board to
> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
> work.
Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related clock
(signal named ECLKOUT or similar) used for anything? If so, then it could be
synchronous, depending on where the signal is routed on the daughtercard. If not,
then it's an asynchronous interface and your DSP EMIF registers should be set up
appropriately.
In the data sheet (see comments below), there is an IFCONFIG Register that has a bit
set for ASYNC or SYNC operation. During normal (working) operation, what is that bit
set to?
> I also know by speaking to the manufacturer (Avnet), the board
> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
> and I was hoping to bring down the EMIFA frequency seperately. Is this
> possible?
Cypress has evidently obsoleted the CY7C68001 device, but I found this data sheet:
http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
On page 13, it discusses internal vs. external clock. It could be that the
daughtercard uses an external clock from the DSK board in order to derive or comply
with correct USB bus timings, so if you deviate then things fall apart. But I would
think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't be used
with a wide range of DSK boards.
Another possibility is an issue with software that Avnet provides for the DSK6416 DSK
-- some timing loop or other code that depends on a 600 MHz clock. Not sure, just
some guesses...
-Jeff
> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> > Charley-
> >
> >> I have a peripheral device that was designed to run with an EMIF
> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> >> down to 100MHz via the on-board dip switches, but those switches also
> >> brings down CPU frequency. I want the CPU frequency to remain the same
> >> (1Ghz).
> >>
> >> I already did a search in the archives here and what I have tried so
> >> far is to adjust some values in the DSP/BIOS config file. I tried
> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> >> really help but am I headed in the right direction?
> >>
> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> >> space.
> >
> > What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> > contains asynchronous devices or interfaces, then clock doesn't matter.
> >
> > -Jeff
> >
> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
> behaves as a slave to the DSP and connects to the external memory
> interface and external perpipheral interface connectors.
>
> I thought it was an asychronous device, but when I set the board to
> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
> work.
Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related clock
(signal named ECLKOUT or similar) used for anything? If so, then it could be
synchronous, depending on where the signal is routed on the daughtercard. If not,
then it's an asynchronous interface and your DSP EMIF registers should be set up
appropriately.
In the data sheet (see comments below), there is an IFCONFIG Register that has a bit
set for ASYNC or SYNC operation. During normal (working) operation, what is that bit
set to?
> I also know by speaking to the manufacturer (Avnet), the board
> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
> and I was hoping to bring down the EMIFA frequency seperately. Is this
> possible?
Cypress has evidently obsoleted the CY7C68001 device, but I found this data sheet:
http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
On page 13, it discusses internal vs. external clock. It could be that the
daughtercard uses an external clock from the DSK board in order to derive or comply
with correct USB bus timings, so if you deviate then things fall apart. But I would
think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't be used
with a wide range of DSK boards.
Another possibility is an issue with software that Avnet provides for the DSK6416 DSK
-- some timing loop or other code that depends on a 600 MHz clock. Not sure, just
some guesses...
-Jeff
> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower wrote:
> > Charley-
> >
> >> I have a peripheral device that was designed to run with an EMIF
> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
> >> down to 100MHz via the on-board dip switches, but those switches also
> >> brings down CPU frequency. I want the CPU frequency to remain the same
> >> (1Ghz).
> >>
> >> I already did a search in the archives here and what I have tried so
> >> far is to adjust some values in the DSP/BIOS config file. I tried
> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
> >> really help but am I headed in the right direction?
> >>
> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
> >> space.
> >
> > What is on the daughtercard? Why does it use EMIF clock? If the daughtercard
> > contains asynchronous devices or interfaces, then clock doesn't matter.
> >
> > -Jeff
> >
Reply by ●July 22, 20082008-07-22
Hello Charley,
On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> Charley-
>
>> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
>> behaves as a slave to the DSP and connects to the external memory
>> interface and external perpipheral interface connectors.
>>
>> I thought it was an asychronous device, but when I set the board to
>> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
>> work.
Like Jeff indicated, [1] verify sync or async [it's likely async
unless some type of clocked RAM or FIFO is used].
If it is sync "follow the clock".
If it is async, make sure that you have plenty of
setup/strobeWidth/hold for testing [you can take out extra cycles
later]. If this doesn't do it, the slave memory make have a max r/w
rate [ie,needs some 'recovery time' between RDs or WRs.
mikedunn
>
> Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related
> clock
> (signal named ECLKOUT or similar) used for anything? If so, then it could be
> synchronous, depending on where the signal is routed on the daughtercard. If
> not,
> then it's an asynchronous interface and your DSP EMIF registers should be
> set up
> appropriately.
>
> In the data sheet (see comments below), there is an IFCONFIG Register that
> has a bit
> set for ASYNC or SYNC operation. During normal (working) operation, what is
> that bit
> set to?
>
>> I also know by speaking to the manufacturer (Avnet), the board
>> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
>> and I was hoping to bring down the EMIFA frequency seperately. Is this
>> possible?
>
> Cypress has evidently obsoleted the CY7C68001 device, but I found this data
> sheet:
>
> http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
>
> On page 13, it discusses internal vs. external clock. It could be that the
> daughtercard uses an external clock from the DSK board in order to derive or
> comply
> with correct USB bus timings, so if you deviate then things fall apart. But
> I would
> think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't
> be used
> with a wide range of DSK boards.
>
> Another possibility is an issue with software that Avnet provides for the
> DSK6416 DSK
> -- some timing loop or other code that depends on a 600 MHz clock. Not sure,
> just
> some guesses...
>
> -Jeff
>
>> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
>> wrote:
>> > Charley-
>> >
>> >> I have a peripheral device that was designed to run with an EMIF
>> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
>> >> down to 100MHz via the on-board dip switches, but those switches also
>> >> brings down CPU frequency. I want the CPU frequency to remain the same
>> >> (1Ghz).
>> >>
>> >> I already did a search in the archives here and what I have tried so
>> >> far is to adjust some values in the DSP/BIOS config file. I tried
>> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
>> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
>> >> really help but am I headed in the right direction?
>> >>
>> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
>> >> space.
>> >
>> > What is on the daughtercard? Why does it use EMIF clock? If the
>> > daughtercard
>> > contains asynchronous devices or interfaces, then clock doesn't matter.
>> >
>> > -Jeff
>>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> Charley-
>
>> The daughtercard contains a Cypress CY7C68001 USB 2.0 controller. It
>> behaves as a slave to the DSP and connects to the external memory
>> interface and external perpipheral interface connectors.
>>
>> I thought it was an asychronous device, but when I set the board to
>> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it doesn't
>> work.
Like Jeff indicated, [1] verify sync or async [it's likely async
unless some type of clocked RAM or FIFO is used].
If it is sync "follow the clock".
If it is async, make sure that you have plenty of
setup/strobeWidth/hold for testing [you can take out extra cycles
later]. If this doesn't do it, the slave memory make have a max r/w
rate [ie,needs some 'recovery time' between RDs or WRs.
mikedunn
>
> Well, you have to look at the daughtercard schematic. Is a DSP EMIF-related
> clock
> (signal named ECLKOUT or similar) used for anything? If so, then it could be
> synchronous, depending on where the signal is routed on the daughtercard. If
> not,
> then it's an asynchronous interface and your DSP EMIF registers should be
> set up
> appropriately.
>
> In the data sheet (see comments below), there is an IFCONFIG Register that
> has a bit
> set for ASYNC or SYNC operation. During normal (working) operation, what is
> that bit
> set to?
>
>> I also know by speaking to the manufacturer (Avnet), the board
>> was designed for the 600Mhz DSK. The project depends on the 1Ghz CPU
>> and I was hoping to bring down the EMIFA frequency seperately. Is this
>> possible?
>
> Cypress has evidently obsoleted the CY7C68001 device, but I found this data
> sheet:
>
> http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-cy7c68001.pdf
>
> On page 13, it discusses internal vs. external clock. It could be that the
> daughtercard uses an external clock from the DSK board in order to derive or
> comply
> with correct USB bus timings, so if you deviate then things fall apart. But
> I would
> think Avnet engineers wouldn't do this, otherwise the daughtercard couldn't
> be used
> with a wide range of DSK boards.
>
> Another possibility is an issue with software that Avnet provides for the
> DSK6416 DSK
> -- some timing loop or other code that depends on a 600 MHz clock. Not sure,
> just
> some guesses...
>
> -Jeff
>
>> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
>> wrote:
>> > Charley-
>> >
>> >> I have a peripheral device that was designed to run with an EMIF
>> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can bring it
>> >> down to 100MHz via the on-board dip switches, but those switches also
>> >> brings down CPU frequency. I want the CPU frequency to remain the same
>> >> (1Ghz).
>> >>
>> >> I already did a search in the archives here and what I have tried so
>> >> far is to adjust some values in the DSP/BIOS config file. I tried
>> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I tried
>> >> adjusting R/W strobe widths, R/W setup widths. These adjustments didn't
>> >> really help but am I headed in the right direction?
>> >>
>> >> My peripheral is a daughtercard so it connects to EMIFA at CE2 and CE3
>> >> space.
>> >
>> > What is on the daughtercard? Why does it use EMIF clock? If the
>> > daughtercard
>> > contains asynchronous devices or interfaces, then clock doesn't matter.
>> >
>> > -Jeff
>>
--
www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
Reply by ●July 22, 20082008-07-22
Okay, after looking at the data sheet, it's definitely asynchronous.
And according to the dsp/bios, all the r/w strobe/setup/hold widths
are set to the maximum values.
How do I make sure the slave memory has a max r/w rate? What should I
look for?
Looking at the bits in the IFCONFIG register, it seems that it set to
external clock and asynchronous, but I don't know how to access the
registers on the the usb controller or if they were even actually
set. The registers look like they have been initialized randomly
(consecutively) like this all the way through
#define IFCONFIG 0x0001
#define FLAGSAB 0x0002
#define FLAGSCD 0x0003
#define POLAR 0x0004
#define REVID 0x0005
So I guess my question is, how do I set the registers?
--- In c..., "Michael Dunn" wrote:
>
> Hello Charley,
>
> On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> > Charley-
> >
> >> The daughtercard contains a Cypress CY7C68001 USB 2.0
controller. It
> >> behaves as a slave to the DSP and connects to the external memory
> >> interface and external perpipheral interface connectors.
> >>
> >> I thought it was an asychronous device, but when I set the board
to
> >> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it
doesn't
> >> work.
>
>
> Like Jeff indicated, [1] verify sync or async [it's likely async
> unless some type of clocked RAM or FIFO is used].
> If it is sync "follow the clock".
> If it is async, make sure that you have plenty of
> setup/strobeWidth/hold for testing [you can take out extra cycles
> later]. If this doesn't do it, the slave memory make have a max r/w
> rate [ie,needs some 'recovery time' between RDs or WRs.
>
> mikedunn
> >
> > Well, you have to look at the daughtercard schematic. Is a DSP
EMIF-related
> > clock
> > (signal named ECLKOUT or similar) used for anything? If so, then
it could be
> > synchronous, depending on where the signal is routed on the
daughtercard. If
> > not,
> > then it's an asynchronous interface and your DSP EMIF registers
should be
> > set up
> > appropriately.
> >
> > In the data sheet (see comments below), there is an IFCONFIG
Register that
> > has a bit
> > set for ASYNC or SYNC operation. During normal (working)
operation, what is
> > that bit
> > set to?
> >
> >> I also know by speaking to the manufacturer (Avnet), the board
> >> was designed for the 600Mhz DSK. The project depends on the 1Ghz
CPU
> >> and I was hoping to bring down the EMIFA frequency seperately.
Is this
> >> possible?
> >
> > Cypress has evidently obsoleted the CY7C68001 device, but I found
this data
> > sheet:
> >
> > http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-
cy7c68001.pdf
> >
> > On page 13, it discusses internal vs. external clock. It could be
that the
> > daughtercard uses an external clock from the DSK board in order
to derive or
> > comply
> > with correct USB bus timings, so if you deviate then things fall
apart. But
> > I would
> > think Avnet engineers wouldn't do this, otherwise the
daughtercard couldn't
> > be used
> > with a wide range of DSK boards.
> >
> > Another possibility is an issue with software that Avnet provides
for the
> > DSK6416 DSK
> > -- some timing loop or other code that depends on a 600 MHz
clock. Not sure,
> > just
> > some guesses...
> >
> > -Jeff
> >
> >> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
> >> wrote:
> >> > Charley-
> >> >
> >> >> I have a peripheral device that was designed to run with an
EMIF
> >> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can
bring it
> >> >> down to 100MHz via the on-board dip switches, but those
switches also
> >> >> brings down CPU frequency. I want the CPU frequency to remain
the same
> >> >> (1Ghz).
> >> >>
> >> >> I already did a search in the archives here and what I have
tried so
> >> >> far is to adjust some values in the DSP/BIOS config file. I
tried
> >> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I
tried
> >> >> adjusting R/W strobe widths, R/W setup widths. These
adjustments didn't
> >> >> really help but am I headed in the right direction?
> >> >>
> >> >> My peripheral is a daughtercard so it connects to EMIFA at
CE2 and CE3
> >> >> space.
> >> >
> >> > What is on the daughtercard? Why does it use EMIF clock? If the
> >> > daughtercard
> >> > contains asynchronous devices or interfaces, then clock
doesn't matter.
> >> >
> >> > -Jeff
> >> >
> > --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
And according to the dsp/bios, all the r/w strobe/setup/hold widths
are set to the maximum values.
How do I make sure the slave memory has a max r/w rate? What should I
look for?
Looking at the bits in the IFCONFIG register, it seems that it set to
external clock and asynchronous, but I don't know how to access the
registers on the the usb controller or if they were even actually
set. The registers look like they have been initialized randomly
(consecutively) like this all the way through
#define IFCONFIG 0x0001
#define FLAGSAB 0x0002
#define FLAGSCD 0x0003
#define POLAR 0x0004
#define REVID 0x0005
So I guess my question is, how do I set the registers?
--- In c..., "Michael Dunn" wrote:
>
> Hello Charley,
>
> On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> > Charley-
> >
> >> The daughtercard contains a Cypress CY7C68001 USB 2.0
controller. It
> >> behaves as a slave to the DSP and connects to the external memory
> >> interface and external perpipheral interface connectors.
> >>
> >> I thought it was an asychronous device, but when I set the board
to
> >> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it
doesn't
> >> work.
>
>
> Like Jeff indicated, [1] verify sync or async [it's likely async
> unless some type of clocked RAM or FIFO is used].
> If it is sync "follow the clock".
> If it is async, make sure that you have plenty of
> setup/strobeWidth/hold for testing [you can take out extra cycles
> later]. If this doesn't do it, the slave memory make have a max r/w
> rate [ie,needs some 'recovery time' between RDs or WRs.
>
> mikedunn
> >
> > Well, you have to look at the daughtercard schematic. Is a DSP
EMIF-related
> > clock
> > (signal named ECLKOUT or similar) used for anything? If so, then
it could be
> > synchronous, depending on where the signal is routed on the
daughtercard. If
> > not,
> > then it's an asynchronous interface and your DSP EMIF registers
should be
> > set up
> > appropriately.
> >
> > In the data sheet (see comments below), there is an IFCONFIG
Register that
> > has a bit
> > set for ASYNC or SYNC operation. During normal (working)
operation, what is
> > that bit
> > set to?
> >
> >> I also know by speaking to the manufacturer (Avnet), the board
> >> was designed for the 600Mhz DSK. The project depends on the 1Ghz
CPU
> >> and I was hoping to bring down the EMIFA frequency seperately.
Is this
> >> possible?
> >
> > Cypress has evidently obsoleted the CY7C68001 device, but I found
this data
> > sheet:
> >
> > http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-
cy7c68001.pdf
> >
> > On page 13, it discusses internal vs. external clock. It could be
that the
> > daughtercard uses an external clock from the DSK board in order
to derive or
> > comply
> > with correct USB bus timings, so if you deviate then things fall
apart. But
> > I would
> > think Avnet engineers wouldn't do this, otherwise the
daughtercard couldn't
> > be used
> > with a wide range of DSK boards.
> >
> > Another possibility is an issue with software that Avnet provides
for the
> > DSK6416 DSK
> > -- some timing loop or other code that depends on a 600 MHz
clock. Not sure,
> > just
> > some guesses...
> >
> > -Jeff
> >
> >> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
> >> wrote:
> >> > Charley-
> >> >
> >> >> I have a peripheral device that was designed to run with an
EMIF
> >> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can
bring it
> >> >> down to 100MHz via the on-board dip switches, but those
switches also
> >> >> brings down CPU frequency. I want the CPU frequency to remain
the same
> >> >> (1Ghz).
> >> >>
> >> >> I already did a search in the archives here and what I have
tried so
> >> >> far is to adjust some values in the DSP/BIOS config file. I
tried
> >> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I
tried
> >> >> adjusting R/W strobe widths, R/W setup widths. These
adjustments didn't
> >> >> really help but am I headed in the right direction?
> >> >>
> >> >> My peripheral is a daughtercard so it connects to EMIFA at
CE2 and CE3
> >> >> space.
> >> >
> >> > What is on the daughtercard? Why does it use EMIF clock? If the
> >> > daughtercard
> >> > contains asynchronous devices or interfaces, then clock
doesn't matter.
> >> >
> >> > -Jeff
> >> >
> > --
> www.dsprelated.com/blogs-1/nf/Mike_Dunn.php
>
Reply by ●July 22, 20082008-07-22
Charley-
> Okay, after looking at the data sheet, it's definitely asynchronous.
> And according to the dsp/bios, all the r/w strobe/setup/hold widths
> are set to the maximum values.
I think you are correct, but the CY7C68001 data sheet by itself doesn't tell you
whether the device is being used in sync or async mode. This chip supports both
types of interface.
> How do I make sure the slave memory has a max r/w rate? What should I
> look for?
The Avnet software that comes with the daughtercard should include some examples that
a) configure EMIF registers to support the daughtercard, and b) configure CY7C68001
registers. Look for EMIF register settings in this code. You can try to minimize
timing, for example reduce wait-states.
> Looking at the bits in the IFCONFIG register, it seems that it set to
> external clock and asynchronous, but I don't know how to access the
> registers on the the usb controller or if they were even actually
> set. The registers look like they have been initialized randomly
> (consecutively) like this all the way through
>
> #define IFCONFIG 0x0001
> #define FLAGSAB 0x0002
> #define FLAGSCD 0x0003
> #define POLAR 0x0004
> #define REVID 0x0005
>
> So I guess my question is, how do I set the registers?
I haven't looked at the Avnet card since 2005, but it's possible the Avnet software
includes one or more APIs specifically intended for setting registers on the device.
You should look over the Avnet APIs very carefully. If not, then my suggestion is to
pick an API that does something like "initialize" or "set" as an example, and 'follow
the code' from the API through the Avnet driver and onto the daughtercard. From that
you should be able to determine how to set registers on your own.
-Jeff
> --- In c..., "Michael Dunn" wrote:
> >
> > Hello Charley,
> >
> > On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> > > Charley-
> > >
> > >> The daughtercard contains a Cypress CY7C68001 USB 2.0
> controller. It
> > >> behaves as a slave to the DSP and connects to the external memory
> > >> interface and external perpipheral interface connectors.
> > >>
> > >> I thought it was an asychronous device, but when I set the board
> to
> > >> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it
> doesn't
> > >> work.
> >
> >
> > Like Jeff indicated, [1] verify sync or async [it's likely async
> > unless some type of clocked RAM or FIFO is used].
> > If it is sync "follow the clock".
> > If it is async, make sure that you have plenty of
> > setup/strobeWidth/hold for testing [you can take out extra cycles
> > later]. If this doesn't do it, the slave memory make have a max r/w
> > rate [ie,needs some 'recovery time' between RDs or WRs.
> >
> > mikedunn
> > >
> > > Well, you have to look at the daughtercard schematic. Is a DSP
> EMIF-related
> > > clock
> > > (signal named ECLKOUT or similar) used for anything? If so, then
> it could be
> > > synchronous, depending on where the signal is routed on the
> daughtercard. If
> > > not,
> > > then it's an asynchronous interface and your DSP EMIF registers
> should be
> > > set up
> > > appropriately.
> > >
> > > In the data sheet (see comments below), there is an IFCONFIG
> Register that
> > > has a bit
> > > set for ASYNC or SYNC operation. During normal (working)
> operation, what is
> > > that bit
> > > set to?
> > >
> > >> I also know by speaking to the manufacturer (Avnet), the board
> > >> was designed for the 600Mhz DSK. The project depends on the 1Ghz
> CPU
> > >> and I was hoping to bring down the EMIFA frequency seperately.
> Is this
> > >> possible?
> > >
> > > Cypress has evidently obsoleted the CY7C68001 device, but I found
> this data
> > > sheet:
> > >
> > > http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-
> cy7c68001.pdf
> > >
> > > On page 13, it discusses internal vs. external clock. It could be
> that the
> > > daughtercard uses an external clock from the DSK board in order
> to derive or
> > > comply
> > > with correct USB bus timings, so if you deviate then things fall
> apart. But
> > > I would
> > > think Avnet engineers wouldn't do this, otherwise the
> daughtercard couldn't
> > > be used
> > > with a wide range of DSK boards.
> > >
> > > Another possibility is an issue with software that Avnet provides
> for the
> > > DSK6416 DSK
> > > -- some timing loop or other code that depends on a 600 MHz
> clock. Not sure,
> > > just
> > > some guesses...
> > >
> > > -Jeff
> > >
> > >> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
> > >> wrote:
> > >> > Charley-
> > >> >
> > >> >> I have a peripheral device that was designed to run with an
> EMIF
> > >> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can
> bring it
> > >> >> down to 100MHz via the on-board dip switches, but those
> switches also
> > >> >> brings down CPU frequency. I want the CPU frequency to remain
> the same
> > >> >> (1Ghz).
> > >> >>
> > >> >> I already did a search in the archives here and what I have
> tried so
> > >> >> far is to adjust some values in the DSP/BIOS config file. I
> tried
> > >> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I
> tried
> > >> >> adjusting R/W strobe widths, R/W setup widths. These
> adjustments didn't
> > >> >> really help but am I headed in the right direction?
> > >> >>
> > >> >> My peripheral is a daughtercard so it connects to EMIFA at
> CE2 and CE3
> > >> >> space.
> > >> >
> > >> > What is on the daughtercard? Why does it use EMIF clock? If the
> > >> > daughtercard
> > >> > contains asynchronous devices or interfaces, then clock
> doesn't matter.
> > >> >
> > >> > -Jeff
> Okay, after looking at the data sheet, it's definitely asynchronous.
> And according to the dsp/bios, all the r/w strobe/setup/hold widths
> are set to the maximum values.
I think you are correct, but the CY7C68001 data sheet by itself doesn't tell you
whether the device is being used in sync or async mode. This chip supports both
types of interface.
> How do I make sure the slave memory has a max r/w rate? What should I
> look for?
The Avnet software that comes with the daughtercard should include some examples that
a) configure EMIF registers to support the daughtercard, and b) configure CY7C68001
registers. Look for EMIF register settings in this code. You can try to minimize
timing, for example reduce wait-states.
> Looking at the bits in the IFCONFIG register, it seems that it set to
> external clock and asynchronous, but I don't know how to access the
> registers on the the usb controller or if they were even actually
> set. The registers look like they have been initialized randomly
> (consecutively) like this all the way through
>
> #define IFCONFIG 0x0001
> #define FLAGSAB 0x0002
> #define FLAGSCD 0x0003
> #define POLAR 0x0004
> #define REVID 0x0005
>
> So I guess my question is, how do I set the registers?
I haven't looked at the Avnet card since 2005, but it's possible the Avnet software
includes one or more APIs specifically intended for setting registers on the device.
You should look over the Avnet APIs very carefully. If not, then my suggestion is to
pick an API that does something like "initialize" or "set" as an example, and 'follow
the code' from the API through the Avnet driver and onto the daughtercard. From that
you should be able to determine how to set registers on your own.
-Jeff
> --- In c..., "Michael Dunn" wrote:
> >
> > Hello Charley,
> >
> > On Mon, Jul 21, 2008 at 9:25 PM, Jeff Brower wrote:
> > > Charley-
> > >
> > >> The daughtercard contains a Cypress CY7C68001 USB 2.0
> controller. It
> > >> behaves as a slave to the DSP and connects to the external memory
> > >> interface and external perpipheral interface connectors.
> > >>
> > >> I thought it was an asychronous device, but when I set the board
> to
> > >> 600Mhz/100Mhz it works, when I set the board to 1Ghz/125Mhz it
> doesn't
> > >> work.
> >
> >
> > Like Jeff indicated, [1] verify sync or async [it's likely async
> > unless some type of clocked RAM or FIFO is used].
> > If it is sync "follow the clock".
> > If it is async, make sure that you have plenty of
> > setup/strobeWidth/hold for testing [you can take out extra cycles
> > later]. If this doesn't do it, the slave memory make have a max r/w
> > rate [ie,needs some 'recovery time' between RDs or WRs.
> >
> > mikedunn
> > >
> > > Well, you have to look at the daughtercard schematic. Is a DSP
> EMIF-related
> > > clock
> > > (signal named ECLKOUT or similar) used for anything? If so, then
> it could be
> > > synchronous, depending on where the signal is routed on the
> daughtercard. If
> > > not,
> > > then it's an asynchronous interface and your DSP EMIF registers
> should be
> > > set up
> > > appropriately.
> > >
> > > In the data sheet (see comments below), there is an IFCONFIG
> Register that
> > > has a bit
> > > set for ASYNC or SYNC operation. During normal (working)
> operation, what is
> > > that bit
> > > set to?
> > >
> > >> I also know by speaking to the manufacturer (Avnet), the board
> > >> was designed for the 600Mhz DSK. The project depends on the 1Ghz
> CPU
> > >> and I was hoping to bring down the EMIFA frequency seperately.
> Is this
> > >> possible?
> > >
> > > Cypress has evidently obsoleted the CY7C68001 device, but I found
> this data
> > > sheet:
> > >
> > > http://www1.cs.columbia.edu/~sedwards/classes/2005/4840/cypress-
> cy7c68001.pdf
> > >
> > > On page 13, it discusses internal vs. external clock. It could be
> that the
> > > daughtercard uses an external clock from the DSK board in order
> to derive or
> > > comply
> > > with correct USB bus timings, so if you deviate then things fall
> apart. But
> > > I would
> > > think Avnet engineers wouldn't do this, otherwise the
> daughtercard couldn't
> > > be used
> > > with a wide range of DSK boards.
> > >
> > > Another possibility is an issue with software that Avnet provides
> for the
> > > DSK6416 DSK
> > > -- some timing loop or other code that depends on a 600 MHz
> clock. Not sure,
> > > just
> > > some guesses...
> > >
> > > -Jeff
> > >
> > >> On Mon, Jul 21, 2008 at 2:13 PM, Jeff Brower
> > >> wrote:
> > >> > Charley-
> > >> >
> > >> >> I have a peripheral device that was designed to run with an
> EMIF
> > >> >> frequency of 100MHz. My DSK runs at 125MHz by default. I can
> bring it
> > >> >> down to 100MHz via the on-board dip switches, but those
> switches also
> > >> >> brings down CPU frequency. I want the CPU frequency to remain
> the same
> > >> >> (1Ghz).
> > >> >>
> > >> >> I already did a search in the archives here and what I have
> tried so
> > >> >> far is to adjust some values in the DSP/BIOS config file. I
> tried
> > >> >> changing ECLKOUT2 to 1/2x EMIF input, and 1/4x EMIF input. I
> tried
> > >> >> adjusting R/W strobe widths, R/W setup widths. These
> adjustments didn't
> > >> >> really help but am I headed in the right direction?
> > >> >>
> > >> >> My peripheral is a daughtercard so it connects to EMIFA at
> CE2 and CE3
> > >> >> space.
> > >> >
> > >> > What is on the daughtercard? Why does it use EMIF clock? If the
> > >> > daughtercard
> > >> > contains asynchronous devices or interfaces, then clock
> doesn't matter.
> > >> >
> > >> > -Jeff
