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Power On Reset Issue

Started by smankan August 13, 2008
Gentlemen,

I am using TMS320C6412 DSP and I found that during power-on reset
the values were correct in the pci memory mapped I/O registers but
the JTAG id and DEVSTAT register was showing corrupt values but when
I do the Manual reset using a switch, the JTAG id and DEVSTAT
register are correct and pci memory mapped I/O register values get
set to 0s.

Is this normal to for the pci memory mapped I/O register values to
get set to 0s on Manual reset? According to the PCI manual, EEAI bit
is set to 1 on power-on reset as well as on hard-reset, is thie
correct? So why EEAI in pci memory mapped I/O register value gets
set to 0 instead of 1 when hard reset is done.

What is the power-on reset timing requirements, I am using tps3106?
Is tps3106 fine for power-on & manual reset requirement.

Currently my only issue is during power-on reset, the JTAG id and
DEVSTAT register are showing corrupt values and that is changing
the "endianess etc" configuration and I am not able to download the
code & I need to hit Manual reset which causes the PC to hang &
resets all pci memory mapped I/O register values to 0.

Is it normal for PC to hang on manual reset??

Your help is appreciated.
S Mankan-

> I am using TMS320C6412 DSP and I found that during power-on reset
> the values were correct in the pci memory mapped I/O registers but
> the JTAG id and DEVSTAT register was showing corrupt values but when
> I do the Manual reset using a switch, the JTAG id and DEVSTAT
> register are correct and pci memory mapped I/O register values get
> set to 0s.
>
> Is this normal to for the pci memory mapped I/O register values to
> get set to 0s on Manual reset? According to the PCI manual, EEAI bit
> is set to 1 on power-on reset as well as on hard-reset, is thie
> correct? So why EEAI in pci memory mapped I/O register value gets
> set to 0 instead of 1 when hard reset is done.
>
> What is the power-on reset timing requirements, I am using tps3106?
> Is tps3106 fine for power-on & manual reset requirement.
>
> Currently my only issue is during power-on reset, the JTAG id and
> DEVSTAT register are showing corrupt values and that is changing
> the "endianess etc" configuration and I am not able to download the
> code & I need to hit Manual reset which causes the PC to hang &
> resets all pci memory mapped I/O register values to 0.
>
> Is it normal for PC to hang on manual reset??

One guess is that your power-on Reset is not held long enough, and there are some
pull-up/down R chip config inputs that are not fully stabilized when Reset is
de-asserted. You might try looking at power-on Reset curve vs. manual Reset curve on
the scope and see if there is obvious difference in timing or shape.

-Jeff