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Stanley- > I'm facing a situation that I wanna to sent a parallel port interface control > signal to my daughterboard by using the programmable array logic (Module U18_PALB) > on the C6711 DSK, but I just can't find any relevant software settings from the CSL > and the CCS help file was not explained very clear on it. Do you know any TI > literatures that deals on setting this parallel control signal, if possible could > you just reply me the literature number to me, thanks a lot!!! You need the C6211dsk.hlp or C6711dsk.hlp files. All DSK board PAL equations are in there, including U18 and U20; I believe the help files are installed on your PC on c:\ti\docs\hlp or pdf subdirs or similar. If you go to the following page, you can find all of the DSK board documentation for DSK C6211: http://koala.ece.rice.edu/elec424/docs/ Be careful, there are some differences with DSK C6711, as pointed out recently by Tom Dillon of TI; if you search the group archives on the subject of "schematics", you will see more info. Below I've cut-pasted the U18 equations from the C6211dsk.hlp file. Good luck. Jeff Brower DSP sw/hw engineer Signalogic MODULE U18_PALBTITLE ' PAL NAME: PALB PAL #: U18, 940* DWG NAME: TMS320C6211 DSP Starter Kit (DSK) ASSY #: D600940-0001* COMPANY: Texas Instruments IncorporatedSYNTHESIS TOOL: Synario Project Navigator version 4.10' U18 device 'P22V10C'; "The PALLV22V10 is a 28-pin PLCC"DESCRIPTION "This module controls the C6211 DSK resets, I/O port reads/writes, "and daughterboard buffers direction & output signals."Inputs ECLK pin 2; "DSP EMIF CLocK (AKA, ECLKOUT in other docs.) PPC_TBC_RST_ pin 3; "PPC's Test Bus Controller ReSeT PPC_SRST_ pin 4; "Parallel Port Controller (PPC) Software ReSeT SVS_RST_ pin 5; "Supply Voltage Supervisor ReSeT PPC_DSP_RST_ pin 6; "PPC's Digital Signal Processor ReSeT PBSW_RST_ pin 7; "Push Button SWitch ReSeT CE1_ pin 9; "Chip Enable 1 from the DSP's EMIF CE2_ pin 10; "Chip Enable 2 from the DSP's EMIF CE3_ pin 11; "Chip Enable 3 from the DSP's EMIF AOE_ pin 12; "Asynchronous Output Enable from the DSP's EMIF "Shown as SDRAS_/AOE_ in the schematics ARE_ pin 13; "Asynchronous Read Enable from the DSP's EMIF "Shown as SDCAS_/ARE_ in the schematics3 AWE_ pin 16; "Asynchronous Write Enable from the DSP's EMIF "Shown as SDWE_/AWE_ in the schematics EA19 pin 27; "Splits CE1 space in two "Low = Flash ROM address space "High = I/O port address space"Outputs DSK_RST_ pin 17; "DSK board-level ReSeT TBC_RST_ pin 18; "Test Bus Controller ReSeT MAN_RST_ pin 19; "MANual ReSeT to voltage supervisor DSP_RST_ pin 20; "Digital Signal Processor ReSeT CE1_ROM_ pin 21; "CE1 Read-Only Memory chip enable RD_IOPORT_ pin 23; "ReaD the I/O PORT (direction signal) WR_IOPORT pin 24; "WRite the I/O PORT (direction signal) DB_OE_ pin 25; "DaughterBoard Output Enable DB_DIR pin 26; "DaughterBoard DIRection"Constants h,l,x = 1, 0, .X. ;EQUATIONS "------------------------------ "Signals output from this PAL can reset the entire board, the DSP, "or the JTAG TBC. All resets are asserted upon power-up, when the "manual reset pushbutton switch is pressed or when the board is in "a software board reset under control of the host. "MANual ReSeT "Asserted when the PPC's software reset or the DSK's reset "pushbutton is depressed. This debounced reset signal is fed back "to the SVS as input which in turn is used to generate the actual "reset signal(s) using SVS_RST_. "NOTE: PBSW_RST_ will bounce during reset pushbutton use, but the " TPS3307 supply voltage supervisor provides a debounce by " holding its reset output active for 200 ms (typically) after " the last low value. " !MAN_RST_ = !PPC_SRST_ # !PBSW_RST_; !MAN_RST_ = !PBSW_RST_; "DSK ReSeT "Resets the PPC, daughterboard, and analog interface circuit !DSK_RST_ = !SVS_RST_; "DSP ReSeT "Resets the DSP only !DSP_RST_ = !PPC_DSP_RST_ # !SVS_RST_; "TBC ReSeT "Resets the TBC only !TBC_RST_ = !PPC_TBC_RST_ # !SVS_RST_; "------------------------------ "I/O port reads/writes are done by decoding the DSP's EMIF address "line EA19. The DSP's CE1 (chip enable space 1) address space is "divided into two by decoding EA19; the lower half addresses the "Flash ROM and the upper half addresses the I/O port ('374 device). "Other logic determines the I/O port mode as either read or write. "Enables the ROM in CE1 space !CE1_ROM_ = !CE1_ & !EA19; "ReaD the I/O PORT !RD_IOPORT_ = !CE1_ & EA19 & !ARE_; "WRite the I/O PORT WR_IOPORT = !CE1_ & EA19 & !AWE_; "------------------------------ "Daughterboard buffers direction and output logic determines "whether daughterboard buffers are output enabled. It also "determines whether the buffers are in read (daughterboard to DSK) "or write (DSK to daughterboard) mode. "DaughterBoard Output Enable "Low = output to DB enabled "High = output to DB disabled !DB_OE_ = (!CE2_ $ !CE3_); "DaughterBoard DIRection "Low = write DB data bus "High = read DB data bus DB_DIR = !ARE_; "TEST_VECTORS - Reset circuitry vectors TBD "([ PPC_SRST_, PBSW_RST_ ] -> MAN_RST_ ) " [ Inputs ] -> Output;Result " [ 0, 0 ] -> 1; " " [ 0, 1 ] -> 0; " " [ 1, 0 ] -> 1; " " [ 1, 1 ] -> 0; "TEST_VECTORS ([ CE1_, EA19 ] -> CE1_ROM_ ) "[ Inputs ] -> Output;Result [ 0, 0 ] -> 0; "Pass [ 0, 1 ] -> 1; "Pass "[ 1, 0 ] -> 0; ""Fail [ 1, 1 ] -> 1; "PassTEST_VECTORS ([ CE1_, EA19, ARE_ ] -> RD_IOPORT_ ) "[ Inputs ] -> Output;Result " [ 1, 0, 0 ] -> 0; ""Fail [ 1, 0, 1 ] -> 1; "Pass "[ 1, 1, 0 ] -> 0; ""Fail [ 1, 1, 1 ] -> 1; "Pass [ 0, 0, 0 ] -> 1; "Pass [ 0, 0, 1 ] -> 1; "Pass [ 0, 1, 0 ] -> 0; "Pass "[ 0, 1, 1 ] -> 0; ""FailTEST_VECTORS ([ CE1_, EA19, AWE_ ] -> WR_IOPORT ) "[ Inputs ] -> Output;Result "[ 0, 0, 0 ] -> 1; ""Fail "[ 0, 0, 1 ] -> 1; ""Fail [ 0, 1, 0 ] -> 1; "Pass [ 0, 1, 1 ] -> 0; "Pass [ 1, 0, 0 ] -> 0; "Pass "[ 1, 0, 1 ] -> 1; ""Fail [ 1, 1, 0 ] -> 0; "Pass "[ 1, 1, 1 ] -> 1; ""FailTEST_VECTORS ([ CE2_, CE3_ ] -> DB_OE_ ) "[ Inputs ] -> Output;Result "[ 0, 0 ] -> 0; ""Fail "[ 0, 1 ] -> 1; ""Fail [ 1, 0 ] -> 0; "Pass [ 1, 1 ] -> 1; "Pass [ 0, 1 ] -> 0; "PassTEST_VECTORS ([ ARE_ ] -> DB_DIR ) "[ Input] -> Output;Result "[ 0 ] -> 0; ""Fail "[ 1 ] -> 1; ""Fail [ 0 ] -> 1; "Pass"Correct simulation results are as follows when fail vectors aren't commented:"..*.*.*....***...*.***...**. " "Warning: only 16 out of 28 vectors passed."Correct simulation results are as follows when fail vectors are commented: " "16 out of 16 vectors passed. END |
Re: PAL on the C6711 DSK
Started by ●October 24, 2002
