Hi,
This post is related to my post on cache without the BIOS in the C6424.
I've got a working engineering demo (audio portion of an MPEG video
encoder used for broadcast) of an application running well on the
C6424 with the BIOS and McASP HWI using the BIOS. The McASP HWI's are
using a lot of CPU cycles for the audio samples so off to using the
EDMA3 I went. I've got the EDMA3 working well in my DMA test project
not using the BIOS. As soon as I try it with the BIOS the transmitted
data is garbage (all buffer pointers seem to be correct, etc). I have
not yet looked at the received data since I've not been able to get
this to work yet. I'm not an expert on the BIOS and all of it's
capabilities.
I'm basically boxed into a corner here where my application runs to
slow without the BIOS and the DMA isn't working with the BIOS. I'm
told by TI that only a register layer CSL exists for the C6424 which
at first seemed like it excluded using the CSL for the cache...?
I need to either the cache working without the BIOS OR the DMA working
with the BIOS ASAP!
Any further help would be greatly appreciated!
Jim
EDMA3 working without BIOS, data is garbage with BIOS
Started by ●December 16, 2008
Reply by ●December 16, 20082008-12-16
Jim-
> This post is related to my post on cache without the BIOS in the C6424.
>
> I've got a working engineering demo (audio portion of an MPEG video
> encoder used for broadcast) of an application running well on the
> C6424 with the BIOS and McASP HWI using the BIOS. The McASP HWI's are
> using a lot of CPU cycles for the audio samples so off to using the
> EDMA3 I went. I've got the EDMA3 working well in my DMA test project
> not using the BIOS. As soon as I try it with the BIOS the transmitted
> data is garbage (all buffer pointers seem to be correct, etc). I have
> not yet looked at the received data since I've not been able to get
> this to work yet. I'm not an expert on the BIOS and all of it's
> capabilities.
>
> I'm basically boxed into a corner here where my application runs to
> slow without the BIOS and the DMA isn't working with the BIOS.
Where are you trying to DMA to/from when using DSP/BIOS? Suggest to experiment first
with DMA to internal SRAM (making sure that's not an area used by L2 cache). Once
you get that working, then you can DMA to SDRAM, as I assume is required if you are
processing a substantial amount of video data. But that's more complex, as you must
deal with cache coherency issues.
> I'm
> told by TI that only a register layer CSL exists for the C6424 which
> at first seemed like it excluded using the CSL for the cache...?
Can you clarify? What exactly did TI tell you?
> I need to either the cache working without the BIOS OR the DMA working
> with the BIOS ASAP!
It should be straightforward to configure and enable cache using CSL without
DSP/BIOS. Did you try CSL functions like:
CACHE_enableCaching()
CACHE_setL2Mode()
What happens? Can the project build?
-Jeff
> This post is related to my post on cache without the BIOS in the C6424.
>
> I've got a working engineering demo (audio portion of an MPEG video
> encoder used for broadcast) of an application running well on the
> C6424 with the BIOS and McASP HWI using the BIOS. The McASP HWI's are
> using a lot of CPU cycles for the audio samples so off to using the
> EDMA3 I went. I've got the EDMA3 working well in my DMA test project
> not using the BIOS. As soon as I try it with the BIOS the transmitted
> data is garbage (all buffer pointers seem to be correct, etc). I have
> not yet looked at the received data since I've not been able to get
> this to work yet. I'm not an expert on the BIOS and all of it's
> capabilities.
>
> I'm basically boxed into a corner here where my application runs to
> slow without the BIOS and the DMA isn't working with the BIOS.
Where are you trying to DMA to/from when using DSP/BIOS? Suggest to experiment first
with DMA to internal SRAM (making sure that's not an area used by L2 cache). Once
you get that working, then you can DMA to SDRAM, as I assume is required if you are
processing a substantial amount of video data. But that's more complex, as you must
deal with cache coherency issues.
> I'm
> told by TI that only a register layer CSL exists for the C6424 which
> at first seemed like it excluded using the CSL for the cache...?
Can you clarify? What exactly did TI tell you?
> I need to either the cache working without the BIOS OR the DMA working
> with the BIOS ASAP!
It should be straightforward to configure and enable cache using CSL without
DSP/BIOS. Did you try CSL functions like:
CACHE_enableCaching()
CACHE_setL2Mode()
What happens? Can the project build?
-Jeff
Reply by ●December 18, 20082008-12-18
Jim-
> Thanks for the reply!
> I seem to be a little stuck for the moment.
> The project will not compile due to there being no ".lib" file in the CSL for the C6424 and/or there being no
> CHIP_6424 (there is CHIP_6418 etc) defined in the header files. This is also the case for the PSP when it comes to the
> cache header files (etc).
You can enter CHIP_6424 into the "Pre-Define Symbol (-d)" box under Build Options | Compiler | Preprocessor tab.
> I'm implementing the audio (Dolby Digital AC3) portion using the C6424.
> I like your idea of using the non-cached internal memory area since I don't need much memory.
Well if you have enough internal mem space that's fine, but in general if you're going to have some SDRAM in your
final product it's not a bad idea to place there "relatively infrequently accessed data". Leaves room for critical
stuff in internal mem -- which every project seems to eventually find a need for.
-Jeff
PS. Please post to the group, not to me. If you want to cc me that's fine.
> When looking for an example HWI without the BIOS for the C6424 I was told the following by TI:
>
> -----------------
> Jim,
>
> Thank you for contacting Texas
> Instruments Technical Support. The Service Request #1-615549809 has been
> assigned to your inquiry.
>
> The DM642 used a functional layer
> CSL whereas the C6424 uses a combination of register layer CSL and PSP (Platform
> Support Package) as its software suite. The functional CSL was created
> specifically for the older DSPs and is configured for the memory map on those
> parts. Because the C6424 contains an entirely different CPU Core, peripheral set
> and memory map the older CSL software will not work.
>
> I do not know of
> any examples that completely exclude DSP/BIOS from the project, but there is a
> GPIO Interrupt example using the register layer CSL and BIOS for C6424 which can
> be found at the link below. I hope that this is of some use, but please let me
> know if this is not what you are looking for.
>
> https://www-a.ti.com/downloads/sds_support/applications_packages/csl3x_reglayer_examples/index.htm
>
>
> --------------------
>
> --- On Tue, 12/16/08, Jeff Brower wrote:
> From: Jeff Brower
> Subject: Re: [c6x] EDMA3 working without BIOS, data is garbage with BIOS
> To: "Jim Haberly"
> Cc: c...
> Date: Tuesday, December 16, 2008, 10:55 AM
>
> Jim-
>
>> This post is related to my post on cache without the BIOS in the C6424.
>>
>> I've got a working engineering demo (audio portion of an MPEG video
>> encoder used for broadcast) of an application running well on the
>> C6424 with the BIOS and McASP HWI using the BIOS. The
> McASP HWI's are
>> using a lot of CPU cycles for the audio samples so off to using the
>> EDMA3 I went. I've got the EDMA3 working well in my DMA test project
>> not using the BIOS. As soon as I try it with the BIOS the transmitted
>> data is garbage (all buffer pointers seem to be correct, etc). I have
>> not yet looked at the received data since I've not been able to get
>> this to work yet. I'm not an expert on the BIOS and all of it's
>> capabilities.
>>
>> I'm basically boxed into a corner here where my application runs to
>> slow without the BIOS and the DMA isn't working with the BIOS.
>
> Where are you trying to DMA to/from when using DSP/BIOS? Suggest to experiment
> first
> with DMA to internal SRAM (making sure that's not an area used by L2
> cache). Once
> you get that working, then you can DMA to SDRAM, as I assume is required if you
> are
> processing a substantial amount of
> video data. But that's more complex, as
> you must
> deal with cache coherency issues.
>
>> I'm
>> told by TI that only a register layer CSL exists for the C6424 which
>> at first seemed like it excluded using the CSL for the cache...?
>
> Can you clarify? What exactly did TI tell you?
>
>> I need to either the cache working without the BIOS OR the DMA working
>> with the BIOS ASAP!
>
> It should be straightforward to configure and enable cache using CSL without
> DSP/BIOS. Did you try CSL functions like:
>
> CACHE_enableCaching()
>
> CACHE_setL2Mode()
>
> What happens? Can the project build?
>
> -Jeff
> Thanks for the reply!
> I seem to be a little stuck for the moment.
> The project will not compile due to there being no ".lib" file in the CSL for the C6424 and/or there being no
> CHIP_6424 (there is CHIP_6418 etc) defined in the header files. This is also the case for the PSP when it comes to the
> cache header files (etc).
You can enter CHIP_6424 into the "Pre-Define Symbol (-d)" box under Build Options | Compiler | Preprocessor tab.
> I'm implementing the audio (Dolby Digital AC3) portion using the C6424.
> I like your idea of using the non-cached internal memory area since I don't need much memory.
Well if you have enough internal mem space that's fine, but in general if you're going to have some SDRAM in your
final product it's not a bad idea to place there "relatively infrequently accessed data". Leaves room for critical
stuff in internal mem -- which every project seems to eventually find a need for.
-Jeff
PS. Please post to the group, not to me. If you want to cc me that's fine.
> When looking for an example HWI without the BIOS for the C6424 I was told the following by TI:
>
> -----------------
> Jim,
>
> Thank you for contacting Texas
> Instruments Technical Support. The Service Request #1-615549809 has been
> assigned to your inquiry.
>
> The DM642 used a functional layer
> CSL whereas the C6424 uses a combination of register layer CSL and PSP (Platform
> Support Package) as its software suite. The functional CSL was created
> specifically for the older DSPs and is configured for the memory map on those
> parts. Because the C6424 contains an entirely different CPU Core, peripheral set
> and memory map the older CSL software will not work.
>
> I do not know of
> any examples that completely exclude DSP/BIOS from the project, but there is a
> GPIO Interrupt example using the register layer CSL and BIOS for C6424 which can
> be found at the link below. I hope that this is of some use, but please let me
> know if this is not what you are looking for.
>
> https://www-a.ti.com/downloads/sds_support/applications_packages/csl3x_reglayer_examples/index.htm
>
>
> --------------------
>
> --- On Tue, 12/16/08, Jeff Brower wrote:
> From: Jeff Brower
> Subject: Re: [c6x] EDMA3 working without BIOS, data is garbage with BIOS
> To: "Jim Haberly"
> Cc: c...
> Date: Tuesday, December 16, 2008, 10:55 AM
>
> Jim-
>
>> This post is related to my post on cache without the BIOS in the C6424.
>>
>> I've got a working engineering demo (audio portion of an MPEG video
>> encoder used for broadcast) of an application running well on the
>> C6424 with the BIOS and McASP HWI using the BIOS. The
> McASP HWI's are
>> using a lot of CPU cycles for the audio samples so off to using the
>> EDMA3 I went. I've got the EDMA3 working well in my DMA test project
>> not using the BIOS. As soon as I try it with the BIOS the transmitted
>> data is garbage (all buffer pointers seem to be correct, etc). I have
>> not yet looked at the received data since I've not been able to get
>> this to work yet. I'm not an expert on the BIOS and all of it's
>> capabilities.
>>
>> I'm basically boxed into a corner here where my application runs to
>> slow without the BIOS and the DMA isn't working with the BIOS.
>
> Where are you trying to DMA to/from when using DSP/BIOS? Suggest to experiment
> first
> with DMA to internal SRAM (making sure that's not an area used by L2
> cache). Once
> you get that working, then you can DMA to SDRAM, as I assume is required if you
> are
> processing a substantial amount of
> video data. But that's more complex, as
> you must
> deal with cache coherency issues.
>
>> I'm
>> told by TI that only a register layer CSL exists for the C6424 which
>> at first seemed like it excluded using the CSL for the cache...?
>
> Can you clarify? What exactly did TI tell you?
>
>> I need to either the cache working without the BIOS OR the DMA working
>> with the BIOS ASAP!
>
> It should be straightforward to configure and enable cache using CSL without
> DSP/BIOS. Did you try CSL functions like:
>
> CACHE_enableCaching()
>
> CACHE_setL2Mode()
>
> What happens? Can the project build?
>
> -Jeff
