> Subject Re: working on dm642 with pci
> Posted by: "Michael Dunn" m...@gmail.com mikedunn.0101
> Date: Mon Jan 26, 2009 1:03 pm ((PST))
>
> Paul,
>
> On Mon, Jan 26, 2009 at 12:31 PM, wrote:
>> Hi,
>>
>> I saw this old thread on a forum and wanted to ask you if you resolved the
>> problem you were having with the code starting to execute?
>>
>> I have a similar problem myself with the DM642, except that I am using the
>> HPI interface to load my software on a bespoke PCB design.
>>
>> The steps I follow are:
>> 1. Take the processor out of reset and into host boot mode.
>> 2. Configure the EMIF.
>> 3. Load the code via the HPI (and verify it is correct).
>> 4. Assert the DSPINT bit in the HPIC register.
>>
>> Everything seems to work fine, but the code does not start executing. I
know
>> the hardware is OK because I can run the code on my emulator. I can also
use
>> the emulator to view the memory space, so I know the code is programmed
and
>> the DSPINT bit is being set.
>
>
> The most common cause of this symptom is the lack of a vector table.
> DSPINT goes to address 0 to execute - when load a program from CCS, it
> goes to the entry point defined in the COFF file. The easiest way to
> fix it is to put a branch to the entry point at address 0.
> Search under the 'examples' dir for 'vec*.asm' for an
example file
> [make sure you use one for 62xx/670x/671x/641x].
> If you are using interrupts, you will need to set those up
> appropriately. If you are not using interrupts at this point, I like
> to plug the unused ones with a branch to self.
>
> mikedunn
>>
>> Any help would be appreciated,
>>
>> Many thanks,
>>
>> Paul.
Hi Paul,
Below is an IST code I used to use in the days I worked with a DM642
hardware.
Later on I have patched it for the large memory model - 32 bit address jumps;
the attached code is the patched one. Small memory model code was using
simple
B LABEL jumps without preserving the target address register on the stack.
(Thanks to Jeff Bower and Mike Dunn and many other people in the c6x group
for
the discussions and hinting me with the idea of how to implement the far
jumps
in the IST).
Rgds,
Andrew
; ----
; vectors.asm
; IST interrupt service table
; Created 05/03/2006
; Modified 06/27/2006
; ----
; ----
; interrupt table selector value description
; ----
; INT0 RESET ---- ------ RESET interrupt
; INT1 NMI ---- ------ NON-MASKABLE intrrupt
; INT2 RESERVED ---- ------ RESERVED
; INT3 RESERVED ---- ------ RESERVED
; INT4 EXTP4 0x04 (00100) EXT PIN 4 interrupt
; *** INT5 EXTP5 0x05 (00101) EXT PIN 5 interrupt
; INT5 * VP0INT 0x19 (11001) VP0 interrupt
; INT6 * VP1INT 0x1A (11010) VP1 interrupt
; INT7 * VP2INT 0x1B (11011) VP2 interrupt
; INT8 EDMAINT 0x08 (01000) EDMA interrupt
; INT9 * ARINT0 0x1D (11101) MCASP0 receive interrupt
; INT10 Not used
; INT11 SWI --- ------ Software interrupt
; INT12 * I2C 0x16 (10110) I2C interrupt
; INT13 * PCI 0x00 (00000) PCI (HOST-TO-DSP) interrupt
; INT14 * TINT0 0x01 (00001) TIMER 0 interrupt
; INT15 TINT1 0x02 (00010) TIMER 1 interrupt
; ----
; PCI: DSP-TO-HOST interrupt is asserted in PCI ISR
; ----
; ----
; unmapped interrups selector value description
; ----
; TINT2 0x13 (10011) TIMER 2 interrupt
; SWI 0x07 (00111) software interrupt
(EXTINT7)
; ----
; ----
; MACRO DEFINITIONS
; ----
.ASG A15, FP ; frame pointer
.ASG B14, DP ; data page pointer
.ASG B15, SP ; stack pointer (grows down first
unused)
; ----
; macro unused interrupts
; inifinite loop with nested branches to disable interrupts
; for all undefined vectors
; ----
UNUSED .MACRO ID ; begin macro
.GLOBAL ID ;
ID: B .S2 ID ; nested branches to block interrupts
NOP 4 ;
B .S2 ID ;
NOP ;
NOP ;
NOP ;
NOP ;
NOP ;
.ENDM ; end macro
; ----
; ISR macro: jump to ISR (interrupt service routine)
; Parameters:
; ID: macro identificator
; REF: ISR entry address label
; ----
ISR .MACRO ID, REF ; begin macro
.GLOBAL ID ;
.GLOBAL REF ;
ID: STW .D2 B3, *SP--(8) ; save B3 on stack (8 byte aligned)
MVKL .S2 REF, B3 ; 16 LSB of ISR address
MVKH .S2 REF, B3 ; 16 MSB of ISR address
B .S2 B3 ; jump to ISR
LDW .D2 *++SP(8), B3 ; restore B3 from stack
NOP 1 ; jump delay slots 2
NOP 1 ; --- 3
NOP 2 ; --- 4, 5
.ENDM ; end macro
; ----
; global ISR labels
; ----
; .REF _c_int00 ; RESET (INT0)
; .REF _ISR_VP0 ; VP0 (INT5)
; .REF _ISR_VP1 ; VP1 (INT6)
; .REF _ISR_VP2 ; VP2 (INT7)
; .REF _ISR_EDMA ; EDMA (INT8)
; .REF _ISR_MCASP0 ; MCASP0 (INT9)
; .REF _ISR_I2C ; I2C (INT12)
; .REF _ISR_PCI ; PCI (INT13)
; .REF _ISR_TIMER0 ; TIMER0 (INT14)
; .REF _ISR_TIMER1 ; TIMER1 (INT15)
; ----
.SECT ".vectors"
; ----
; RESET
; ----
.REF _c_int00
RESET: ; (RESET)
MVKL .S2 _c_int00, B3 ; 16 LSB
MVKH .S2 _c_int00, B3 ; 16 MSB
B .S2 B3 ; jump to _c_int00
NOP 1 ;
NOP 1 ;
NOP 1 ;
NOP 1 ;
NOP 1 ;
; ----
; NMI (INT1)
; ----
UNUSED NMI ; (NMI)
; ----
; RESV1 (INT2)
; ----
UNUSED RESV1 ; (INT2)
; ----
; RESV2 (INT3)
; ----
UNUSED RESV2 ; (INT3)
; ----
; INT4 EXTP4 ISR
; ----
; UNUSED INT4 ; (INT4)
ISR INT4, _ISR_EXTP4 ; EXTP4 (INT4)
; ----
; INT5 VP0 ISR
; ----
ISR INT5, _ISR_VP0 ; VP1 (INT5)
; ----
; INT6 VP1 ISR
; ----
ISR INT6, _ISR_VP1 ; VP1 (INT6)
; ----
; INT7 VP2 ISR
; ----
ISR INT7, _ISR_VP2 ; VP2 (INT7)
; ----
; INT8 EDMA ISR
; ----
ISR INT8, _ISR_EDMA ; EDMA (INT8)
; ----
; INT9 MCASP0 ISR
; ----
ISR INT9, _ISR_MCASP0 ; MCASP0 (INT9)
; ----
; INT10
; ----
UNUSED INT10 ; (INT10)
; ----
; INT11
; ----
UNUSED INT11 ; (INT11)
; ----
; INT12 I2C ISR
; ----
ISR INT12, _ISR_I2C ; I2C (INT12)
; ----
; INT13 HOST-TO-DSP ISR
; ----
ISR INT13, _ISR_PCI ; PCI (INT13)
; ----
; INT14 TIMER0 ISR
; ----
ISR INT14, _ISR_TIMER0 ; TIMER 0 (INT14)
; ----
; INT15 TIMER1 ISR
; ----
ISR INT15, _ISR_TIMER1 ; TIMER 1 (INT15)
; ----
; plug in unused interrupts with infinite loops
; to catch astray interrupts
; ----
; UNUSED NMI ; (NMI)
; UNUSED RESV1 ; (INT2)
; UNUSED RESV2 ; (INT3)
; UNUSED INT4 ; (INT4)
; UNUSED INT5 ; (INT5)
; UNUSED INT6 ; (INT6)
; UNUSED INT7 ; (INT7)
; UNUSED INT8 ; (INT8)
; UNUSED INT9 ; (INT9)
; UNUSED INT10 ; (INT10)
; UNUSED INT11 ; (INT11)
; UNUSED INT12 ; (INT12)
; UNUSED INT13 ; (INT13)
; UNUSED INT14 ; (INT14)
; UNUSED INT15 ; (INT15)
; ----
;
.END
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